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| this is information on a product in full production. september 2016 docid027107 rev 6 1/202 stm32f446xc/e arm ? cortex ? -m4 32b mcu+fpu, 225dmips, up to 512kb flash/128+4kb ram, usb otg hs/fs, 17 tims, 3 adcs, 20 comm. interfaces datasheet - production data features ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from fl ash memory, frequency up to 180 mhz, mpu, 225 dmips/1.25 dmips/mhz (dhrystone 2.1), and dsp instructions ? memories ? 512 kb of flash memory ? 128 kb of sram ? flexible external memory controller with up to 16-bit data bus: sram,psram,sdram/lpsdr sdram, flash nor/nand memories ? dual mode quad spi interface ? lcd parallel interface, 8080/6800 modes ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc, 2032 bit backup registers + optional 4 kb backup sram ? 312-bit, 2.4 msps adc: up to 24 channels and 7.2 msps in trip le interleaved mode ? 212-bit d/a converters ? general-purpose dma: 16-stream dma controller with fifos and burst support ? up to 17 timers: 2x watchdog, 1x systick timer and up to twelve 16-bit and two 32-bit timers up to 180 mhz, each with up to 4 ic/oc/pwm or pulse counter ? debug mode ? swd & jtag interfaces ?cortex ? -m4 trace macrocell? ? up to 114 i/o ports with interrupt capability ? up to 111 fast i/os up to 90 mhz ? up to 112 5 v-tolerant i/os ? up to 20 communica tion interfaces ? spdif-rx ? up to 4 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/2 uarts (11.25 mbit/s, iso7816 interface, lin, irda, modem control) ? up to 4 spis (45 mbits/s), 3 with muxed i 2 s for audio class accuracy via internal audio pll or external clock ? 2 x sai (serial audio interface) ? 2 can (2.0b active) ? sdio interface ? consumer electronics control (cec) i/f ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? dedicated usb power rail enabling on-chip phys operation throughout the entire mcu power supply range ? 8- to 14-bit parallel camera interface up to 54 mbytes/s ? crc calculation unit ? rtc: subsecond accuracy, hardware calendar ? 96-bit unique id table 1. device summary reference part number stm32f446xc/e stm32f446mc, STM32F446ME, stm32f446rc, stm32f446re, stm32f446vc, stm32f446ve, stm32f446zc, stm32f446ze. lqfp64 (10 10mm) lqfp100 (14 14mm) lqfp144 (20 x 20 mm) ufbga144 (7 x 7 mm) & " ' ! ufbga144 (10 x 10 mm) wlcsp 81 www.st.com
contents stm32f446xc/e 2/202 docid027107 rev 6 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 compatibility with stm32f4 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 arm ? cortex ? -m4 with fpu and embedded flash and sram . . . . . . . 17 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 17 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18 3.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 flexible memory controller (fmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 quad spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.3 regulator on/off and inte rnal reset on/off availability . . . . . . . . . . 27 3.18 real-time clock (rtc), backup sram and backup registers . . . . . . . . . . 28 3.19 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.20 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.21 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 docid027107 rev 6 3/202 stm32f446xc/e contents 5 3.21.1 advanced-control timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21.4 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21.5 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23 universal synchronous/asynchronous re ceiver transmitters (usart) . . 34 3.24 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.25 hdmi (high-definition multimedia interface) consumer electronics control (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.26 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.27 spdif-rx receiver interface (spdifrx) . . . . . . . . . . . . . . . . . . . . . . . . 35 3.28 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.29 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.30 serial audio interface pll(pllsai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.31 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . . . 36 3.32 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.33 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 37 3.34 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . . . 37 3.35 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.36 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.37 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.38 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.39 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.40 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.41 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 contents stm32f446xc/e 4/202 docid027107 rev 6 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.2 vcap_1/vcap_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 79 6.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 79 6.3.5 reset and power control block characterist ics . . . . . . . . . . . . . . . . . . . 80 6.3.6 over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.8 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.9 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.10 internal clock source char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.11 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.12 pll spread spectrum clock generatio n (sscg) characteristics . . . . . 110 6.3.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.14 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.15 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 116 6.3.16 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.17 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.18 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.19 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.20 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.21 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.24 reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.25 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.26 fmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.3.27 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 172 6.3.28 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 173 6.3.29 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 docid027107 rev 6 5/202 stm32f446xc/e contents 5 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.1 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.2 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.3 lqfp144 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.4 ufbga144 7 x 7 mm package information . . . . . . . . . . . . . . . . . . . . . . 186 7.5 ufbga144 10 x 10 mm package information . . . . . . . . . . . . . . . . . . . . 189 7.6 wlcsp81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.7 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 appendix a application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 a.1 usb otg full speed (fs) interface solutions . . . . . . . . . . . . . . . . . . . . . 197 a.2 usb otg high speed (hs) interface solutions . . . . . . . . . . . . . . . . . . . . 199 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 list of figures stm32f446xc/e 6/202 docid027107 rev 6 list of figures figure 1. compatible board design for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. compatible board for lqfp64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. stm32f446xc/e block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 4. stm32f446xc/e and multi-ahb matr ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. vddusb connected to an external independent po wer supply . . . . . . . . . . . . . . . . . . . . . 23 figure 6. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 24 figure 7. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. startup in regulator off: slow v dd slope power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. startup in regulator off mode: fast v dd slope power-down reset risen before v cap_1 /v cap_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. stm32f446xc/xe lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11. stm32f446xc/xe lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12. stm32f446xc lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 13. stm32f446xc/xe wlcsp81 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14. stm32f446xc/xe ufbga144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 16. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 17. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 18. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 19. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 20. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 21. typical v bat current consumption (rtc on/backup ram off and lse in low power mode) . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 22. typical v bat current consumption (rtc on/backup ram off and lse in high drive mode). . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 23. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 24. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 25. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 figure 26. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 27. lacc hsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 28. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 29. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 30. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 31. ft i/o input ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 32. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 33. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 34. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 35. fmpi 2 c timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 36. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 37. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 38. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 31 figure 39. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 40. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 41. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 42. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 43. usb otg full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 138 figure 44. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 docid027107 rev 6 7/202 stm32f446xc/e list of figures 7 figure 45. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 46. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 47. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 146 figure 48. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 147 figure 49. 12-bit buffered/non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 50. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 153 figure 51. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 155 figure 52. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 156 figure 53. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 158 figure 54. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 55. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 56. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 57. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 58. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 59. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 60. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 168 figure 61. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 168 figure 62. sdram read access waveforms (c l = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 63. sdram write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 figure 64. dcmi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 65. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 66. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 67. lqfp64-10x10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 176 figure 68. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 69. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 70. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 179 figure 71. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 72. lqfp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 73. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 182 figure 74. lqfp144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 75. lqfp144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 76. ufbga144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 77. ufbga144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footpr int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 78. uqfp144 7 x 7 mm marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . 188 figure 79. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 80. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package recommended footpr int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 figure 81. uqfp144 10 x 10 mm marking example (package top view). . . . . . . . . . . . . . . . . . . . . . 191 figure 82. wlcsp81 - 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 83. wlcsp81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 84. wlcsp81 10 x 10 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . . 194 figure 85. usb controller configured as peripheral-only and used in full speed mode . . . . . . . . . . 197 figure 86. usb controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 197 figure 87. usb controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 198 figure 88. usb controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 list of tables stm32f446xc/e 8/202 docid027107 rev 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f446xc/e features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 25 table 4. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 10. stm32f446xx pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 11. alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 12. stm32f446xc/e register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 13. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 14. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 15. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 16. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 17. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 78 table 18. vcap_1/vcap_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 19. operating conditions at power-up/power-down (reg ulator on) . . . . . . . . . . . . . . . . . . . . . 79 table 20. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 79 table 21. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 22. over-drive switching characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 23. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram . . . . . . . 83 table 24. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled with prefetch) or ram . . . . . . . . . 84 table 25. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 26. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 86 table 27. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 89 table 28. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 90 table 29. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 91 table 30. typical current consumption in run mode, code with data processing running from flash memory or ram, regulator on (art accelerator enabled except prefetch), vdd=1.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 31. typical current consumption in run mode, code with data processing running from flash memory, regulator off (art accelera tor enabled except pref etch). . . . . . . . 94 table 32. typical current consumption in sleep mode, regulator on, vdd=1.7 v . . . . . . . . . . . . . . 95 table 33. typical current consumption in sleep mode, regula tor off. . . . . . . . . . . . . . . . . . . . . . . . 96 table 34. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 35. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 36. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 37. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 38. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 39. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 40. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 41. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 42. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 docid027107 rev 6 9/202 stm32f446xc/e list of tables 10 table 43. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 44. plli2s (audio pll) characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 09 table 45. pllisai characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 46. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 47. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 48. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 49. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 50. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 51. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 52. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 53. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 table 54. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 55. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 56. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 57. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 58. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 59. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 60. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 61. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 62. fmpi 2 c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 63. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 64. qspi dynamic characteristics in sdr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 65. qspi dynamic characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 66. i 2 s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 67. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 68. usb otg full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 37 table 69. usb otg full speed dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 70. usb otg full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 71. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 table 72. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 table 73. dynamic characteristics: usb ulpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 74. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 75. adc static accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 76. adc static accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 77. adc static accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 78. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 143 table 79. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 143 table 80. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 table 81. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 82. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 83. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 84. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 85. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 86. asynchronous non-multiplexed sram/psram/nor - read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 87. asynchronous non-multiplexed sram/psram/nor read - nwait timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 88. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 155 table 89. asynchronous non-multiplexed sram/psram/nor write - nwait timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 90. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 91. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 157 list of tables stm32f446xc/e 10/202 docid027107 rev 6 table 92. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 93. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 159 table 94. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 95. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 96. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 164 table 97. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 98. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 99. switching characteristics for na nd flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 100. sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 101. lpsdr sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 70 table 102. sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 103. lpsdr sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 104. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 105. dynamic characteristics: sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 106. dynamic characteristics: emmc characteristi cs vdd = 1.7 v to 1.9 v. . . . . . . . . . . . . . . 175 table 107. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 108. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 176 table 109. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 110. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 183 table 111. ufbga144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 112. ufbga144 recommended pcb design rules (0. 50 mm pitch bga) . . . . . . . . . . . . . . . . 187 table 113. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 114. ufbga144 recommended pcb design rules (0. 80 mm pitch bga) . . . . . . . . . . . . . . . . 190 table 115. wlcsp81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 116. wlcsp81 recommended pcb design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 193 table 117. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 118. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 119. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 docid027107 rev 6 11/202 stm32f446xc/e introduction 40 1 introduction this document provides the descript ion of the stm32f446xc/e products. the stm32f446xc/e document should be read in conjunction with the stm32f4xx reference manual. for information on the cortex ? -m4 core, please refer to the cortex ? -m4 programming manual (pm0214), available from the www.st.com . description stm32f446xc/e 12/202 docid027107 rev 6 2 description the stm32f446xc/e devices are ba sed on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 180 mhz. the cortex-m4 core features a floating point unit (fpu) single precision which supports all arm ? single-precision data- processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f446xc/e devices incorporate high-speed embedded memories (flash memory up to 512 kbyte, up to 128 kbyte of sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/ os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for moto r control, two general-purpose 32-bit timers. they also feature standard and advanced communication interfaces. ? up to four i 2 cs; ? four spis, three i 2 ss full simplex. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audi o pll or via an external clock to allow synchronization; ? four usarts plus two uarts; ? an usb otg full-speed and an usb otg hi gh-speed with full-spe ed capability (with the ulpi), both with ded icated power rails allowing to use them throughout the entire power range; ? two cans; ? two sais serial audio interfaces. to achieve audio class accuracy, the sais can be clocked via a dedicated internal audio pll; ? an sdio/mmc interface; ? camera interface; ? hdmi-cec; ? spdif receiver (spdifrx); ? quadspi. advanced peripherals include an sdio, a flexible memory control (fmc) interface, a camera interface for cm os sensors. refer to table 2: stm32f446xc/e features and peripheral counts for the list of peripherals available on each part number. the stm32f446xc/e devices operates in the ?40 to +105 c temperature range from a 1.7 to 3.6 v power supply. the supply voltage can drop to 1.7 v with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f446xc/e devices offer devices in 6 packages ranging from 64 pins to 144 pins. the set of included peripherals changes with the device chosen. docid027107 rev 6 13/202 stm32f446xc/e description 40 these features make the stm32f446xc/e micr ocontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances table 2. stm32f446xc/e features and peripheral counts peripherals stm32f44 6mc stm32f44 6me stm32f44 6rc stm32f44 6re stm32f44 6vc stm32f44 6ve stm32f44 6zc stm32f44 6ze flash memory in kbytes 256 512 256 512 256 512 256 512 sram in kbytes system 128 (112+16) backup 4 fmc memory controller no yes (1) timers general- purpose 10 advanced- control 2 basic 2 communication interfaces spi / i 2 s 4/3 (simplex) (2) i 2 c 4/1 fmp + usart/uart 4/2 usb otg fs yes (6-endpoints) usb otg hs yes (8-endpoints) can 2 sai 2 sdio yes spdif-rx 1 hdmi-cec 1 quad spi (3) 1 camera interface yes gpios 635081114 12-bit adc number of channels 3 14 16 16 24 12-bit dac number of channels yes 2 maximum cpu frequency 180 mhz operating voltage 1.8 to 3.6 v (4) operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c packages wlcsp81 lqfp64 lqfp100 lqfp144 ufbga144 description stm32f446xc/e 14/202 docid027107 rev 6 2.1 compatibility with stm32f4 family the stm32f446xc/xv is software and feat ure compatible with the stm32f4 family. the stm32f446xc/xv can be used as drop-in replacement of the other stm32f4 products but some slight changes have to be done on the pcb board. figure 1. compatible board design for lqfp100 package 1. for the lqfp100 package, only fmc bank1 or bank2 are available. bank1 can only support a multiplexed nor/psram memory using t he ne1 chip select. bank2 can only support a 16- or 8-bit nand flas h memory using the nce2 chip select. the interrupt line cannot be used since port g is not available in this package. 2. the spi1, spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio m ode. 3. for the lqfp64 package, the quad spi is available with limited features. 4. v dd /v dda minimum value of 1.7 v is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). 0 6 9 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 9 & $ 3 9 6 6 9 ' ' 6 7 0 ) [ [ 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 9 & $ 3 9 ' ' 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 6 6 9 ' ' 9 6 6 3 % docid027107 rev 6 15/202 stm32f446xc/e description 40 figure 2. compatible board for lqfp64 package figure 3 shows the stm32f446xx block diagram. 9 l q f u h d v h g w r ? i ( 6 5 ? r u e h o r z & $ 3 0 6 9 9 6 6 9 6 6 6 7 0 ) [ [ 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 ' ' 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 & $ 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 9 ' ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 9 ' ' 9 6 6 3 % 9 ' ' 9 6 6 9 6 6 9 ' ' description stm32f446xc/e 16/202 docid027107 rev 6 figure 3. stm32f446xc/e block diagram 0 6 9 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 $ $ + % $ 3 % 8 6 $ 5 7 0 % s v ( ; 7 , 7 : . 8 3 $ ) 3 $ 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 % 3 % 8 6 $ 5 7 0 % s v 7 , 0 ( 5 3 : 0 3 : 0 3 : 0 ( 7 5 % . , 1 d v $ ) 8 6 $ 5 7 0 % s v 7 , 0 ( 5 3 : 0 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 & 3 & 8 6 $ 5 7 0 % s v 8 6 $ 5 7 5 ; 7 ; 6 & . 3 : 0 3 : 0 ( 7 5 % . , 1 d v $ ) & 7 6 5 7 6 d v $ ) 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 ' 3 ' 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 ( 3 ( 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 ) 3 ) 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 * 3 * 8 6 $ 5 7 0 % s v 6 3 , , 6 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) $ 3 % 0 + ] $ 3 % 0 + ] $ , 1 f r p p r q w r w k h $ ' & v $ , 1 f r p p r q w r w k h $ ' & 9 ' ' 5 ( ) b $ ' & $ , 1 w r $ ' & & + ( 7 5 d v $ ) 7 , 0 ( 5 & + ( 7 5 d v $ ) 7 , 0 ( 5 & + ( 7 5 d v $ ) 7 , 0 ( 5 & + d v $ ) 7 , 0 ( 5 5 ; 7 ; 6 & . 8 6 $ 5 7 5 ; 7 ; 6 & . & 7 6 5 7 6 d v $ ) 8 6 $ 5 7 5 ; 7 ; d v $ ) 8 $ 5 7 5 ; 7 ; d v $ ) 8 $ 5 7 0 2 6 , 0 , 6 2 6 & . 6 3 , , 6 1 6 6 : 6 0 & . d v $ ) 0 2 6 , 0 , 6 2 6 & . 6 3 , , 6 1 6 6 : 6 0 & . d v $ ) 6 & / 6 ' $ 6 0 % $ / d v $ ) , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ / d v $ ) , & 6 0 % 8 6 7 ; 5 ; e [ & $ 1 7 ; 5 ; e [ & $ 1 ' $ & d v $ ) ' $ & ' $ & d v $ ) ' $ & , 7 ) 7 , 0 ( 5 7 , 0 ( 5 : l q : $ 7 & + ' 2 * . % % . 3 5 $ 0 6 7 $ 0 3 $ / $ 5 0 b 2 8 7 2 6 & b , 1 2 6 & , 1 2 6 & 2 8 7 2 6 & b 2 8 7 1 5 ( 6 ( 7 9 ' ' $ 9 6 6 $ 9 & $ 3 8 6 $ 5 7 0 % s v 8 6 $ 5 7 5 ; 7 ; 6 & . & 7 6 5 7 6 d v $ ) v p f d u g l u ' $ v p f d u g l u ' $ v p f d u g l u ' $ v p f d u g l u ' $ e e e e e e e e & 7 6 5 7 6 d v $ ) 6 ' , 2 0 0 & ' & 0 ' & . d v $ ) 9 % $ 7 w r 9 * 3 ' 0 $ $ + % $ 3 % * 3 ' 0 $ 6 & / 6 ' $ 6 0 % $ / d v $ ) , & 6 0 % 8 6 8 6 $ 5 7 0 % s v * 3 , 2 3 2 5 7 + 3 + - 7 $ * 6 : $ 5 0 & 2 5 7 ( ; 0 0 + ] ' % 8 6 6 % 8 6 , % 8 6 1 9 , & ( 7 0 0 3 8 ) 3 8 - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 ' 2 6 : ' - 7 ' 2 7 5 $ & ( & . 7 5 $ & ( ' 8 6 % ' 0 $ ) , ) 2 2 7 * + 6 9 ' ' 8 6 % 7 2 9 ' ' 8 / 3 , & / . ' ' , 5 6 7 3 1 ; 7 , ' 9 % 8 6 * 3 ' 0 $ 6 w u h d p v ) , ) 2 * 3 ' 0 $ 6 w u h d p v ) , ) 2 ) / $ 6 + n % ) / $ 6 + , ) 6 5 $ 0 . % 6 5 $ 0 . % ( ; 7 0 ( 0 & 7 / ) 0 & 6 5 $ 0 3 6 5 $ 0 1 2 5 ) / $ 6 + 1 $ 1 ' ) / $ 6 + 6 ' 5 $ 0 & / . 1 ( > @ $ > @ ' > @ 1 2 ( 1 1 : ( 1 1 % / > @ 6 ' & / . ( > @ 6 ' 1 ( > @ 1 5 $ 6 1 & $ 6 1 $ ' 9 1 : $ , 7 , 1 7 1 9 ' ' 8 6 % 7 2 9 ' ' , ' 9 % 8 6 & $ 0 ( 5 $ + 6 < 1 & 9 6 < 1 & 3 , ; & . ' , 7 ) 8 6 % 3 + < 2 7 * ) 6 ) , ) 2 $ + % 0 + ] 3 + < ) , ) 2 8 6 $ 5 7 0 % s v 7 ( 0 3 6 ( 1 6 2 5 $ ' & $ ' & $ ' & , ) , ) # 9 ' ' $ # 9 ' ' $ 3 2 5 3 ' 5 # 9 ' ' $ 6 8 3 3 / < 6 8 3 ( 5 9 , 6 , 2 1 3 9 ' 5 h v h w , q w 3 2 5 ; 7 $ / 2 6 & 0 + ] ; 7 $ / n + ] $ + % 3 & / . + & / . 0 $ 1 $ * 7 $ 3 % 3 & / . 5 7 & 5 & + 6 ) & / . 5 & / 6 6 w d q g e \ l q w h u i d f h : ' * . # 9 % $ 7 # 9 ' ' $ $ : 8 5 ( 6 ( 7 & / 2 & . & 7 5 / $ 3 % 3 & / . 3 / / 3 / / 3 / / $ + % 3 & / . 9 ' ' w r 9 9 6 6 9 2 / 7 5 ( * 9 7 2 9 3 2 : ( 5 0 1 * 7 # 9 ' ' 6 7 $ 0 3 % . 3 5 ( * $ + % % 8 6 0 $ 7 5 , ; 6 0 $ 3 % 0 + ] $ + % 0 + ] / 6 / 6 & + d v $ ) 7 , 0 ( 5 & + d v $ ) 7 , 0 ( 5 & + d v $ ) 7 , 0 ( 5 e e e 8 6 $ 5 7 0 % s v 7 , 0 ( 5 & + d v $ ) 8 6 $ 5 7 0 % s v 7 , 0 ( 5 & + d v $ ) e e 8 6 $ 5 7 0 % s v 7 , 0 ( 5 & + d v $ ) e % 2 5 ) , ) 2 6 3 ' , ) b 5 ; > @ d v $ ) 6 3 ' , ) + ' 0 , b & ( & d v $ ) + ' 0 , & ( & 8 6 $ 5 7 0 % s v 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 ' 6 & . ) 6 0 & / . d v $ ) & 5 & 8 6 $ 5 7 0 % s v 6 $ , 6 ' 6 & . ) 6 0 & / . d v $ ) ' l j ) l o w h u ) , ) 2 3 : 5 & 7 / 4 x d g 6 3 , & / . & 6 d & 6 e ' > @ 8 6 $ 5 7 0 % s v 6 $ , ) , ) 2 6 & / 6 ' $ 6 0 % $ / d v $ ) ) 0 3 , & $ + % b ( 0 , ) , ) 2 docid027107 rev 6 17/202 stm32f446xc/e functional overview 40 3 functional overview 3.1 arm ? cortex ? -m4 with fpu and embe dded flash and sram the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu core is a 32-bit risc processor that features exceptional code-efficiency, delivering the high-performanc e expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit ) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f446xc/e family is compatib le with all arm tools and software. figure 3 shows the general block diagra m of the stm32f446xc/e family. note: cortex-m4 with fpu co re is binary compatible with the cortex-m3 core. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 with fpu processors. it balances the inherent performance advantage of the arm ? cortex ? -m4 with fpu over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 225 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 180 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. functional overview stm32f446xc/e 18/202 docid027107 rev 6 3.4 embedded flash memory the devices embed a flash memory of 512kb available for storing programs and data. 3.5 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 embedded sram all devices embed: ? up to 128kbytes of system sram. ram memory is accessed (read/write) at cpu clock speed with 0 wait states. ? 4 kbytes of backup sram this area is accessible only from the cpu. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 3.7 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cpu, dmas, usb hs) and the slaves flash memory, ram, quadspi, fmc, ahb and apb peripherals and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. docid027107 rev 6 19/202 stm32f446xc/e functional overview 40 figure 4. stm32f446xc/e and multi-ahb matrix 3.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. $ 5 0 & r u w h [ 0 * 3 ' 0 $ % x v p d w u l [ 6 , & 2 ' ( ' & 2 ' ( $ & & ( / ) o d v k p h p r u \ , e x v ' e x v 6 e x v ' 0 $ b 3 , ' 0 $ b 0 ( 0 ' 0 $ b 0 ( 0 ' 0 $ b 3 8 6 % b + 6 b 0 - 3 6 $ 3 % $ 3 % 6 6 6 6 6 6 6 * 3 ' 0 $ 8 6 % 2 7 * + 6 $ + % s h u l s k h u d o v $ + % s h u l s k h u d o v ) 0 & h [ w h u q d o 0 h p & w o 4 x d g 6 3 , 6 5 $ 0 . e \ w h 6 5 $ 0 . e \ w h functional overview stm32f446xc/e 20/202 docid027107 rev 6 the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? dac ? sdio ? camera interface (dcmi) ? adc ? sai1/sai2 ? spdif receiver (spdifrx) ? quadspi 3.9 flexible memory controller (fmc) all devices embed an fmc. it has seven chip select outputs supporting the following modes: sdram/lpsdr sdram, sram, psram, nor flash an d nand flash. with the possibility to remap fmc bank 1 (nor/psram 1 and 2) and fmc sdram bank 1/2 in the cortex-m4 code area. functionality overview: ? 8-,16-bit data bus width ? read fifo for sdram controller ? write fifo ? maximum fmc_clk/fmc_sdclk frequency for synchronous accesses is 90 mhz. lcd parallel interface the fmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 quad spi memory interface (quadspi) all devices embed a quad spi memory interface, which is a specialized communication interface targeting single, dual or quad spi flash memories. it can work in direct mode through registers, external flash status r egister polling mode and memory map ped mode. up to 256 mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access. code execution is supported. the opcode an d the frame format are fully programmable. communication can be either in single data rate or dual data rate. docid027107 rev 6 21/202 stm32f446xc/e functional overview 40 3.11 nested vectored in terrupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4 with fpu core. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 3.12 external interrupt/ event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 114 gpios can be connected to the 16 external interrupt lines. 3.13 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is fa ctory-trimmed to offer 1% accura cy at 25 c. the application can then select as system clock either the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failu re. if a failure is detected, the system automatically switches back to the internal rc oscillator and a so ftware interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 180 mhz. similarly, full in terrupt management of the pll clock entry is available when necessary (for example if an indirectly us ed external oscillator fails). several prescalers allow t he configuration of the two ahb buses, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the two ahb buses is 180 mhz while the maximum frequency of the high-speed apb domains is 90 mhz. the maximum allowe d frequency of the low- speed apb domain is 45 mhz. the devices embed a dedicated pll (plli2s) and pllsai which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. functional overview stm32f446xc/e 22/202 docid027107 rev 6 3.14 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory through a serial (uart, i 2 c, can, spi and usb) communi cation interface. refer to application note an2606 for details. 3.15 power supply schemes ? v dd = 1.7 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. note: v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). refer to table 3: voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. ? v ddusb can be connected either to vdd or an external independent power supply (3.0 to 3.6v) for usb transceivers. for example, when device is powered at 1. 8v, an independent power supply 3.3v can be connected to v ddusb . when the v ddusb is connected to a separated power supply, it is independent from v dd or v dda but it must be the last supply to be provided and the first to disappear. the following conditions vddusb must be respected: ? during power-on phase (v dd < vdd_min), vddusb should be always lower than vdd ? during power-down phase (vdd < vdd_mi n), vddusb should be always lower than vdd ? vddusb rising and falling time rate specifications mu st be respected. ? in operating mode phase, v ddusb could be lower or higher than vdd: ? if usb (usb otg_hs/otg_fs) is used, the associated gpios powered by v ddusb are operating between v ddusb_min and v ddusb_max .the v ddusb supply both usb transceiver (usb otg_hs and usb otg_fs). ? if only one usb transceiver is used in the application, the gpios associated to the other usb transceiver are still supplied by v ddusb . ? if usb (usb otg_hs/otg_fs) is not used, the associated gpios powered by v ddusb are operating between v dd_min and v dd_max . docid027107 rev 6 23/202 stm32f446xc/e functional overview 40 figure 5. v ddusb connected to an external independent power supply 3.16 power supply supervisor 3.16.1 internal reset on on packages embedding the pdr_on pin, th e power supply supervisor is enabled by holding pdr_on high. on the other package, the power supply supervisor is always enabled. the device has an integrated power-on reset (por)/ power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process star ts, either to confirm or modify default bor thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.16.2 internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circui try is disabled through the pdr_on pin. an external power supply supervisor should monitor v dd and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on should be connected to vss, to allows device to oper ate down to 1.7v. refer to figure 6: power supply supervisor interconnection with internal reset off . 0 6 9 9 ' ' 8 6 % b 0 , 1 9 ' ' b 0 , 1 w l p h 9 ' ' 8 6 % b 0 $ ; 8 6 % i x q f w l r q d o d u h d 9 ' ' 9 ' ' $ 8 6 % q r q i x q f w l r q d o d u h d 9 ' ' 8 6 % 3 r z h u r q 3 r z h u g r z q 2 s h u d w l q j p r g h 8 6 % q r q i x q f w l r q d o d u h d functional overview stm32f446xc/e 24/202 docid027107 rev 6 figure 6. power supply supervisor interconnection with internal reset off the v dd specified threshold, below which the device must be maintained under reset, is 1.7 v. a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled ? the brownout reset (bor) circuitry must be disabled ? the embedded programmable voltage detector (pvd) is disabled ? v bat functionality is no more available and v bat pin should be connected to v dd . all packages, except for the lq fp100/lqfp64, allow to disable the internal reset through the pdr_on signal. 3.17 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off 3.17.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. w zz k e ^ d d?? &ee? s ^ ^ w z v}? ?] w xd s d?x s d s ??o]?]}v ? ? ? ?]pvo ~}??]}vo d ^???ee s docid027107 rev 6 25/202 stm32f446xc/e functional overview 40 there are three power modes configured by software when the regulator is on: ? mr mode used in run/sleep modes or in stop modes ? in run/sleep mode the mr mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. the over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. ? in stop modes the mr can be configured in two ways during stop mode: mr operates in normal mode (default mode of mr in stop mode) mr operates in under-drive mode (reduced leakage mode). ? lpr is used in the stop modes: the lp regulator mode is configured by software when entering stop mode. like the mr mode, the lpr can be configured in two ways during stop mode: ? lpr operates in normal mode (default mode when lpr is on) ? lpr operates in under-drive mode (reduced leakage mode). ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. refer to table 3 for a summary of voltage regulator modes versus device operating modes. two external ceramic capacitors should be connected on v cap_1 and v cap_2 pin. all packages have the regulator on feature. 3.17.2 regulator off this feature is availa ble only on packages fe aturing the bypass_reg pi n. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v 12 voltage source through v cap_1 and v cap_2 pins. table 3. voltage regulator configuration mode versus device operating mode (1) 1. ?-? means that the corresponding configuration is not available. voltage regulator configuration run mode sleep mode stop mode standby mode normal mode mr mr mr or lpr - over-drive mode (2) 2. the over-drive mode is not available when v dd = 1.7 to 2.1 v. mr mr - - under-drive mode - - mr or lpr - power-down mode ---yes functional overview stm32f446xc/e 26/202 docid027107 rev 6 since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. when the regulator is off, there is no more internal monitoring on v 12 . an external power supply supervisor should be used to monitor the v 12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v 12 power domain. in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin sinc e it allows to reset a part of the v 12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. ? the over-drive and under-drive modes are not available. figure 7. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be k ept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 8 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 9 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application. d l 9 % < 3 $ 6 6 b 5 ( * 9 & $ 3 b 9 & $ 3 b 3 $ 9 9 ' ' 1 5 6 7 9 ' ' $ s s o l f d w l r q u h v h w v l j q d o r s w l r q d o ( [ w h u q d o 9 & $ 3 b s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 & $ 3 b 0 l q 9 9 docid027107 rev 6 27/202 stm32f446xc/e functional overview 40 figure 8. startup in regulator off: slow v dd slope power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 9. startup in regulator off mode: fast v dd slope power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). 3.17.3 regulator on/off and inte rnal reset on/off availability d l i 9 ' ' w l p h 0 l q 9 3 ' 5 9 r u 9 9 & $ 3 b 9 & $ 3 b 9 1 5 6 7 w l p h 9 ' ' w l p h 0 l q 9 9 & $ 3 b 9 & $ 3 b 9 3 $ d v v h u w h g h [ w h u q d o o \ 1 5 6 7 w l p h d l h 3 ' 5 9 r u 9 table 4. regulator on/off and in ternal reset on/off availability package regulator on regulator off internal reset on internal reset off lqfp64 lqfp100 yes no yes no functional overview stm32f446xc/e 28/202 docid027107 rev 6 3.18 real-time clock (rtc), back up sram and backup registers the backup domain includes: ? the real-time clock (rtc) ? 4 kbytes of backup sram ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (in 12/24 hour), we ek day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensa te for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base cl ock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like memory area. it can be used to store data which need to be retained in vbat and standby mode. this memory area is disabled by default to minimize power consumption (see section 3.19: low-power modes ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 3.19: low-power modes ). additional 32-bit registers contain the prog rammable alarm subseconds, seconds, minutes, hours, day, and date. like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. lqfp144 yes no yes pdr_on set to v dd yes pdr_on set to vss ufbga144 yes bypass_reg set to vss yes bypass_reg set to vdd wlcsp81 table 4. regulator on/off and in ternal reset on/off availability package regulator on regulator off internal reset on internal reset off docid027107 rev 6 29/202 stm32f446xc/e functional overview 40 3.19 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal osc illators are disabled. the voltage regulator can be put either in main regulator mode (mr) or in low-power mode (lpr). both modes can be configured as follows (see table 5: voltage regulator modes in stop mode ): ? normal mode (default mode when mr or lpr is enabled) ? under-drive mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. the standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. 3.20 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. table 5. voltage regulator modes in stop mode voltage regulator configuration main regulator (mr) low-power regulator (lpr) normal mode mr on lpr on under-drive mode mr in under-dri ve mode lpr in under-drive mode functional overview stm32f446xc/e 30/202 docid027107 rev 6 note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is not connected to v dd (internal reset off), the v bat functionality is no more available and v bat pin should be connected to v dd . docid027107 rev 6 31/202 stm32f446xc/e functional overview 40 3.21 timers and watchdogs the devices include two advanced-control time rs, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. table 6 compares the features of the advanced-c ontrol, general-purpose and basic timers. table 6. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock (mhz) max timer clock (mhz) (1) advanced- control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 90 180 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 45 90/180 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 45 90/180 tim9 16-bit up any integer between 1 and 65536 no 2 no 90 180 tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 90 180 tim12 16-bit up any integer between 1 and 65536 no 2 no 45 90/180 tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 45 90/180 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 45 90/180 1. the maximum timer clock is either 90 or 180 mhz depending on timpre bit configuration in the rcc_dckcfgr register. functional overview stm32f446xc/e 32/202 docid027107 rev 6 3.21.1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 and tim8 support indepe ndent dma request generation. 3.21.2 general-purpose timers (timx) there are ten synchronized general-purpose timers embedded in the stm32f446xc/e devices (see table 6 for differences). ? tim2, tim3, tim4, tim5 the stm32f446xc/e include 4 full-featured general-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/ou tput compare, pwm or one-pul se mode output. this gives up to 16 input capture/output comp are/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10, tim11, ti m12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels fo r input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. 3.21.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support indepe ndent dma request generation. docid027107 rev 6 33/202 stm32f446xc/e functional overview 40 3.21.4 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 3.21.5 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.21.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 3.22 inter-integrated circuit interface (i 2 c) four i2c bus interfaces can operate in multimaster and slave modes. three i2c can support the standard (up to 100 khz) and fast (up to 400 khz) modes. one i2c can support the standard (up to 100 khz), fast (up to 400 khz) and fast mode plus (up to 1mhz) modes. they (all i2c) support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. the devices also include programmable analog and digital noise filters (see table 7 ). table 7. comparison of i2c analog and digital filters - analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks functional overview stm32f446xc/e 34/202 docid027107 rev 6 3.23 universal synchronous/asynch ronous receiver transmitters (usart) the devices embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and four universal asynchronous receiver transmitters (uart4, and uart5). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to communicate at speeds of up to 11.25 mbit/s . the other available in terfaces communicate at up to 5.62 bit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interf aces can be served by the dma controller. 3.24 serial peripheral interface (spi) the devices feature up to four spis in slave and master modes in full-duplex and simplex communication modes. spi1, and spi4 can communicate at up to 45 mbits/s, spi2 and spi3 can communicate at up to 22.5 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card /mmc modes. all spis can be served by the dma controller. table 8. usart feature comparison (1) usart name standard features modem (rts/cts) lin spi maste r ird a smartcard (iso 7816) max. baud rate in mbit/s (oversamplin g by 16) max. baud rate in mbit/s (oversamplin g by 8) apb mapping usart1 x x x x x x 5.62 11.25 apb2 (max. 90 mhz) usart2 x x x x x x 2.81 5.62 apb1 (max. 45 mhz) usart3 x x x x x x 2.81 5.62 apb1 (max. 45 mhz) uart4 x x x - x - 2.81 5.62 apb1 (max. 45 mhz) uart5 x x x - x - 2.81 5.62 apb1 (max. 45 mhz) usart6 x x x x x x 5.62 11.25 apb2 (max. 90 mhz) 1. x = feature supported. docid027107 rev 6 35/202 stm32f446xc/e functional overview 40 the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. 3.25 hdmi (high-definition mu ltimedia interface) consumer electronics control (cec) the devices embeds a hdmi-cec controller th at provides hardware support of consumer electronics control (cec) (appendix supplement 1 to the hdmi standard). this protocol provides high-level control f unctions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. 3.26 inter-integr ated sound (i 2 s) three standard i 2 s interfaces (multiplexed with spi1, spi2 and spi3) are available. they can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit reso lution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i2sx can be served by the dma controller. 3.27 spdif-rx receiver interface (spdifrx) the spdif-rx peripheral, is designed to receiv e an s/pdif flow compliant with iec-60958 and iec-61937. these standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by dolby or dts (up to 5.1). the main features of the spdif-rx are the following: ? up to 4 inputs available ? automatic symbol rate detection ? maximum symbol rate: 12.288 mhz ? stereo stream from 32 to 192 khz supported ? supports audio iec-60958 and iec-61937, consumer applications ? parity bit management ? communication using dma for audio samples ? communication using dma for contro l and user channel information ? interrupt capabilities the spdif-rx receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. the user can select the wanted spdif input, and when a valid si gnal will be available, the spdif-rx will re-sample the inco ming signal, decode the manc hester stream , recognize frames, sub-frames and blocks elements. it delivers to the cpu decoded data, and associated status flags. functional overview stm32f446xc/e 36/202 docid027107 rev 6 the spdif-rx also offers a signal named spdifrx_frame_sync, which toggles at the s/pdif sub-frame rate that will be used to compute the exact sample ra te for clock drift algorithms. 3.28 serial audio interface (sai) the devices feature two serial audio interf aces (sai1 and sai2). each serial audio interfaces based on two indepe ndent audio sub blocks which can operate as transmitter or receiver with their fifo. many audio protocols are supported by each block: i2s standards, lsb or msb-justified, pcm/dsp, tdm, ac? 97 and spdif output, supporting audio sampling frequencies from 8 khz up to 192 khz. both sub blocks can be configured in master or in slave mode. the sais use a pll to achieve audio class accuracy. in master mode, the master clock can be output to the external dac/codec at 256 times of the sampling frequency. the two sub blocks can be configured in synchronous mode when full-duplex mode is required. sai1 and sa2 can be served by the dma controller. 3.29 audio pll (plli 2 s) the devices feature an additional dedicated pll for audio i 2 s and sai applications. it allows to achieve error-free i 2 s sampling clock accuracy witho ut compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s/sai sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i 2 s/sai flow with an external pll (or codec output). 3.30 serial audio interface pll(pllsai) an additional pll dedicated to audio and usb is used for sai1 and sai2 peripheral in case the plli2s is programmed to achieve another audio sampling frequency (49.152 mhz or 11.2896 mhz) and the audio application requires both sampling frequencies simultaneously. the pllsai is also used to generate the 48mhz clock for usb fs and sdio in case the system pll is programmed with factors not multiple of 48mhz. 3.31 secure digital input/ output interface (sdio) an sd/sdio/mmc host interface is availabl e, that supports multimediacard system specification version 4.2 in three different da tabus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. docid027107 rev 6 37/202 stm32f446xc/e functional overview 40 the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdi o/mmc4.2 card at any one time and a stack of mmc4.1 or previous. 3.32 controller area network (bxcan) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 3.33 universal serial bus on -the-go full-speed (otg_fs) the devices embed an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll co nnected to the hse oscillator. the usb has dedicated power rails allowing its use throughout the entire power range. the major features are: ? combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 6 bidirectional endpoints ? 12 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 3.34 universal serial bus on -the-go high-speed (otg_hs) the devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external phy device connecte d to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll co nnected to the hse oscillator. the usb has dedicated power rails allowing its use throughout the entire power range. functional overview stm32f446xc/e 38/202 docid027107 rev 6 the major features are: ? combined rx and tx fifo size of 1 kbit 35 with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 8 bidirectional endpoints ? 16 host channels with periodic out support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 3.35 digital camera interface (dcmi) the devices embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 94.5 mbyte/s (in 14-bit mode) at 54 mhz. its features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image black & white. 3.36 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling a llowing maximum i/o toggling up to 90 mhz. 3.37 analog-to-digital converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. docid027107 rev 6 39/202 stm32f446xc/e functional overview 40 additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 3.38 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the same input channel as v bat , adc1_in18, which is used to convert the sensor output voltage into a digital value. when the temperature sensor and v bat conversion are enabled at the same time, only v bat conversion is performed. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.39 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 10-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 3.40 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. functional overview stm32f446xc/e 40/202 docid027107 rev 6 debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.41 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f446xx through a small number of etm pi ns to an external hardware trace port analyser (tpa) device. the tpa is connected to a host co mputer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools. docid027107 rev 6 41/202 stm32f446xc/e pinout and pin description 66 4 pinout and pin description figure 10. stm32f446xc/xe lqfp64 pinout 1. the above figure shows the package top view. 9 % $ 7 3 & 2 6 & b , 1 3 + 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 9 ' ' 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 9 & $ 3 b / 4 ) 3 3 & 0 6 9 9 ' ' 9 6 6 9 ' ' 9 6 6 3 + 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 pinout and pin description stm32f446xc/e 42/202 docid027107 rev 6 figure 11. stm32f446xc/xe lqfp100 pinout 1. the above figure shows the package top view. 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 6 3 3 6 $ $ 0 ( / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 6 $ $ 6 3 3 ! 6 2 % & 6 $ $ ! 6 2 % & 0 ! 0 ! 0 ! 6 $ $ 6 3 3 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 6 # ! 0 ? 6 3 3 6 $ $ 6 $ $ 6 3 3 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! - 3 6 , 1 & 0 0 # 0 ( / 3 # ? / 5 4 docid027107 rev 6 43/202 stm32f446xc/e pinout and pin description 66 figure 12. stm32f446xc lqfp144 pinout 1. the above figure shows the package top view. 9 ' ' 3 ' 5 b 2 1 3 ( 3 ( 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 * 9 ' ' 9 6 6 3 * 3 * 3 * 3 * 3 * 3 * 3 ' 3 ' 9 ' ' 9 6 6 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 & 3 & 3 & 3 $ 3 $ 3 ( 9 ' ' 3 ( 9 6 6 3 ( 3 ( 3 $ 3 ( 3 $ 9 % $ 7 3 $ 3 & 3 $ 3 & 3 $ 3 & 3 $ 3 ) 3 & 3 ) 3 & 3 ) 3 & 3 ) 3 & 3 ) 9 ' ' 8 6 % 3 ) 9 6 6 9 6 6 3 * 9 ' ' 3 * 3 ) 3 * 3 ) 3 * 3 ) 3 * 3 ) 3 * 3 ) 3 * 3 + 3 ' 3 + 3 ' 1 5 6 7 9 ' ' 3 & 9 6 6 3 & 3 ' 3 & 3 ' 3 & 3 ' 9 6 6 $ 3 ' 9 ' ' 3 ' 9 5 ( ) 3 ' 9 ' ' $ 3 % 3 $ 3 % 3 $ 3 % 3 $ 3 % 3 $ 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 ) 3 ) 9 ' ' 3 ) 3 ) 3 ) 3 * 3 * 3 ( 3 ( 3 ( 9 6 6 9 ' ' 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 3 % 9 ' ' / 4 ) 3 9 & $ 3 b 9 6 6 d l f 9 & $ 3 b pinout and pin description stm32f446xc/e 44/202 docid027107 rev 6 figure 13. stm32f446xc/xe wlcsp81 ballout 1. the above figure shows the package top view. 0 6 y 9 9 ' ' $ 3 & 3 % % 2 2 7 3 ( 3 % 9 ' ' 3 ' 3 ' 9 6 6 % 3 $ 3 % 9 6 6 9 % $ 7 3 % 3 ' 5 b 2 1 3 ' 3 ' 3 $ & 9 & $ 3 b 3 % 3 % 3 & 3 % 3 & 3 $ 3 ' 3 & ' 3 $ 3 ' 3 ( 3 & 3 ( 1 5 ( 6 ( 7 3 & 3 & 9 ' ' 8 6 % ( 3 $ 3 $ 3 $ 3 + 3 $ 3 & 3 $ 3 $ 3 & ) 3 & 3 % 9 6 6 $ 3 + 3 $ 3 & 3 & 3 $ 3 ' * 3 ' 3 ( 3 $ 3 & 3 $ 9 6 6 3 % 3 % + 3 % 3 ( 3 $ 9 ' ' 3 % 9 ' ' $ 9 6 6 3 % 3 ' 3 % 9 ' ' 3 ( 3 & 3 $ 3 % % < 3 $ 6 6 b 5 ( * 9 & $ 3 b 3 ( - docid027107 rev 6 45/202 stm32f446xc/e pinout and pin description 66 figure 14. stm32f446xc/xe ufbga144 ballout 1. the above picture shows the package top view. 0 6 y 9 3 & $ 3 ( 3 ( 3 % 3 ' 3 % 3 ' 3 $ 3 ( 3 ( 3 $ 3 $ 3 & % 3 ( 3 % 3 * 3 ' 3 % 3 * 3 & 3 ( 3 ( 3 & 3 $ , 3 & & 9 % $ 7 3 % 3 * 3 ' 3 % 3 * 3 & 3 ) 3 ) 9 ' ' 8 6 % 3 $ 3 + ' 9 6 6 % 2 2 7 3 * 3 ' 3 % 3 * 3 ' 9 ' ' 3 ) 3 $ 3 $ 3 + ( 3 ) 3 ' 5 b 2 1 9 6 6 3 ' 9 6 6 3 * 3 ' 3 ) 3 ) 3 & 3 $ 1 5 6 7 ) 3 ) 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 3 ) 9 ' ' 3 & 3 & 3 ) * 3 ) 9 ' ' 9 ' ' 9 & $ 3 b 9 ' ' 9 6 6 9 6 6 3 ) 9 6 6 3 * 3 & + 3 & % < 3 $ 6 6 b 5 ( * 9 & $ 3 b 3 ' 9 6 6 3 ( 3 * 3 & 3 & 3 * 3 * 3 & 9 6 6 $ 3 $ 3 % 3 ( 3 ' 3 * 3 ( 3 * 3 $ 3 & 3 * 3 * 9 5 ( ) . 3 $ 3 ) 3 ( 3 ' 3 * 3 ( 3 ' 3 $ 3 & 3 ' 3 ' 9 5 ( ) / 3 $ 3 ) 3 ( 3 ' 3 ) 3 ( 3 ' 3 $ 3 % 3 % 3 % 9 ' ' $ 0 3 $ 3 ) 3 ( 3 % 3 ) 3 ( 3 % 3 $ 3 % 3 % 3 % - pinout and pin description stm32f446xc/e 46/202 docid027107 rev 6 table 9. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5v tolerant io, i2c fm+ option tta 3.3 v tolerant i/o directly connected to adc b dedicated boot0 pin rst bidirectional reset pin with weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers table 10. stm32f446xx pin and ball descriptions pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 - 1 d7 a3 1 pe2 i/o ft - traceclk, spi4_sck, sai1_mclk_a, quadspi_bk1_io2, fmc_a23, eventout - - 2 d6 a2 2 pe3 i/o ft - traced0, sai1_sd_b, fmc_a19, eventout - - 3 a9 b2 3 pe4 i/o ft - traced1, spi4_nss, sai1_fs_a, fmc_a20, dcmi_d4, eventout - - 4 - b3 4 pe5 i/o ft - traced2, tim9_ch1, spi4_miso, sai1_sck_a, fmc_a21, dcmi_d6, eventout - docid027107 rev 6 47/202 stm32f446xc/e pinout and pin description 66 - 5 - b4 5 pe6 i/o ft - traced3, tim9_ch2, spi4_mosi, sai1_sd_a, fmc_a22, dcmi_d7, eventout - 1 6 b9 c2 6 vbat s - - - - 2 7 c8 a1 7 pc13 i/o ft - eventout tamp_1/wkup1 38c9b18 pc14- osc32_in(pc14) i/o ft - eventout osc32_in 4 9 d9 c1 9 pc15- osc32_out(pc15) i/o ft - eventout osc32_out -- -c310 pf0 i/oft- i2c2_sda, fmc_a0, eventout - -- -c411 pf1 i/oft- i2c2_scl, fmc_a1, eventout - -- -d412 pf2 i/oft- i2c2_smba, fmc_a2, eventout - - - - e2 13 pf3 i/o ft - fmc_a3, eventout adc3_in9 - - - e3 14 pf4 i/o ft - fmc_a4, eventout adc3_in14 - - - e4 15 pf5 i/o ft - fmc_a5, eventout adc3_in15 - 10 - d2 16 vss s - - - - -11 - d317 vdd s-- - - -- -f318 pf6 i/oft- tim10_ch1, sai1_sd_b, quadspi_bk1_io3, eventout adc3_in4 -- -f219 pf7 i/oft- tim11_ch1, sai1_mclk_b, quadspi_bk1_io2, eventout adc3_in5 -- -g320 pf8 i/oft- sai1_sck_b, tim13_ch1, quadspi_bk1_io0, eventout adc3_in6 -- -g221 pf9 i/oft- sai1_fs_b, tim14_ch1, quadspi_bk1_io1, eventout adc3_in7 - - - g1 22 pf10 i/o ft - dcmi_d11, eventout adc3_in8 5 12 e9 d1 23 ph0-osc_in(ph0) i/o ft - eventout osc_in table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 pinout and pin description stm32f446xc/e 48/202 docid027107 rev 6 613f9e124 ph1- osc_out(ph1) i/o ft - eventout osc_out 7 14 d8 f1 25 nrst i/o rs t -- - 815g9h126 pc0 i/oft- sai1_mclk_b, otg_hs_ulpi_stp, fmc_sdnwe, eventout adc123_in10 916 - h227 pc1 i/oft- spi3_mosi/i2s3_sd, sai1_sd_a, spi2_mosi/i2s2_sd, eventout adc123_in11 10 17 e8 h3 28 pc2 i/o ft - spi2_miso, otg_hs_ulpi_dir, fmc_sdne0, eventout adc123_in12 11 18 f8 h4 29 pc3 i/o ft - spi2_mosi/i2s2_sd, otg_hs_ulpi_nxt, fmc_sdcke0, eventout adc123_in13 -19h9 - 30 vdd s-- - - - - g8 - - vss s - - - - 12 20 f7 j1 31 vssa s - - - - - - - k1 - vref- s - - - - - 21 - l1 32 vref+ s - - - - 13 22 h8 m1 33 vdda s - - - - 14 23 j9 j2 34 pa0-wkup(pa0) i/o ft - tim2_ch1/tim2_etr, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, eventout adc123_in0, wkup0/tamp_2 15 24 g7 k2 35 pa1 i/o ft - tim2_ch2, tim5_ch2, usart2_rts, uart4_rx, quadspi_bk1_io3, sai2_mclk_b, eventout adc123_in1 16 25 e7 l2 36 pa2 i/o ft - tim2_ch3, tim5_ch3, tim9_ch1, usart2_tx, sai2_sck_b, eventout adc123_in2 table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 docid027107 rev 6 49/202 stm32f446xc/e pinout and pin description 66 17 26 e6 m2 37 pa3 i/o ft - tim2_ch4, tim5_ch4, tim9_ch2, sai1_fs_a, usart2_rx, otg_hs_ulpi_d0, eventout adc123_in3 18 27 - g4 38 vss s - - - - - - j8 h5 - bypass_reg i ft - - - 19 28 - f4 39 vdd s - - - - 20 29 h7 j3 40 pa4 i/o tc - spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, usart2_ck, otg_hs_sof, dcmi_hsync, eventout adc12_in4, dac_out1 21 30 f6 k3 41 pa5 i/o tc - tim2_ch1/tim2_etr, tim8_ch1n, spi1_sck/i2s1_ck, otg_hs_ulpi_ck, eventout adc12_in5, dac_out2 22 31 g6 l3 42 pa6 i/o ft - tim1_bkin, tim3_ch1, tim8_bkin, spi1_miso, i2s2_mck, tim13_ch1, dcmi_pixclk, eventout adc12_in6 23 32 e5 m3 43 pa7 i/o ft - tim1_ch1n, tim3_ch2, tim8_ch1n, spi1_mosi/i2s1_sd, tim14_ch1, fmc_sdnwe, eventout adc12_in7 24 33 j7 j4 44 pc4 i/o ft - i2s1_mck, spdifrx_in2, fmc_sdne0, eventout adc12_in14 25 34 - k4 45 pc5 i/o ft - usart3_rx, spdifrx_in3, fmc_sdcke0, eventout adc12_in15 table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 pinout and pin description stm32f446xc/e 50/202 docid027107 rev 6 26 35 f5 l4 46 pb0 i/o ft - tim1_ch2n, tim3_ch3, tim8_ch2n, spi3_mosi/i2s3_sd, uart4_cts, otg_hs_ulpi_d1, sdio_d1, eventout adc12_in8 27 36 h6 m4 47 pb1 i/o ft - tim1_ch3n, tim3_ch4, tim8_ch3n, otg_hs_ulpi_d2, sdio_d2, eventout adc12_in9 28 37 j6 j5 48 pb2-boot1 (pb2) i/o ft - tim2_ch4, sai1_sd_a, spi3_mosi/i2s3_sd, quadspi_clk, otg_hs_ulpi_d4, sdio_ck, eventout - - - - m5 49 pf11 i/o ft - sai2_sd_b, fmc_sdnras, dcmi_d12, eventout - - - - l5 50 pf12 i/o ft - fmc_a6, eventout - - - - - 51 vss s - - - - -- -g552 vdd s-- - - -- -k553 pf13 i/oft- fmpi2c1_smba, fmc_a7, eventout - -- -m654 pf14 i/oftf- fmpi2c1_scl, fmc_a8, eventout - -- -l655 pf15 i/oftf- fmpi2c1_sda, fmc_a9, eventout - - - - k6 56 pg0 i/o ft - fmc_a10, eventout - - - - j6 57 pg1 i/o ft - fmc_a11, eventout - - 38 j5 m7 58 pe7 i/o ft - tim1_etr, uart5_rx, quadspi_bk2_io0, fmc_d4, eventout - - 39 h5 l7 59 pe8 i/o ft - tim1_ch1n, uart5_tx, quadspi_bk2_io1, fmc_d5, eventout - - 40 g5 k7 60 pe9 i/o ft - tim1_ch1, quadspi_bk2_io2, fmc_d6, eventout - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 docid027107 rev 6 51/202 stm32f446xc/e pinout and pin description 66 - - - h6 61 vss s - - - - -- -g662 vdd s-- - - - 41 j4 j7 63 pe10 i/o ft - tim1_ch2n, quadspi_bk2_io3, fmc_d7, eventout - - 42 - h8 64 pe11 i/o ft - tim1_ch2, spi4_nss, sai2_sd_b, fmc_d8, eventout - - 43 - j8 65 pe12 i/o ft - tim1_ch3n, spi4_sck, sai2_sck_b, fmc_d9, eventout - - 44 - k8 66 pe13 i/o ft - tim1_ch3, spi4_miso, sai2_fs_b, fmc_d10, eventout - - 45 - l8 67 pe14 i/o ft - tim1_ch4, spi4_mosi, sai2_mclk_b, fmc_d11, eventout - - 46 - m8 68 pe15 i/o ft - tim1_bkin, fmc_d12, eventout - 29 47 h4 m9 69 pb10 i/o ft - tim2_ch3, i2c2_scl, spi2_sck/i2s2_ck, sai1_sck_a, usart3_tx, otg_hs_ulpi_d3, eventout - - - - m10 70 pb11 i/o ft - tim2_ch4, i2c2_sda, usart3_rx, sai2_sd_a, eventout - 30 48 j3 h7 71 vcap_1 s - - - - 31 49 h3 - - vss s - - - - 32 50 j2 g7 72 vdd s - - - - 33 51 g4 m11 73 pb12 i/o ft - tim1_bkin, i2c2_smba, spi2_nss/i2s2_ws, sai1_sck_b, usart3_ck, can2_rx, otg_hs_ulpi_d5, otg_hs_id, eventout - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 pinout and pin description stm32f446xc/e 52/202 docid027107 rev 6 34 52 h2 m12 74 pb13 i/o ft - tim1_ch1n, spi2_sck/i2s2_ck, usart3_cts, can2_tx, otg_hs_ulpi_d6, eventout otg_hs_vbus 35 53 j1 l11 75 pb14 (1) i/o ft - tim1_ch2n, tim8_ch2n, spi2_miso, usart3_rts, tim12_ch1, otg_hs_dm, eventout - 36 54 g3 l12 76 pb15 (1) i/o ft - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi/i2s2_sd, tim12_ch2, otg_hs_dp, eventout - - 55 - l9 77 pd8 i/o ft - usart3_tx, spdifrx_in1, fmc_d13, eventout - - 56 - k9 78 pd9 i/o ft - usart3_rx, fmc_d14, eventout - - 57 - j9 79 pd10 i/o ft - usart3_ck, fmc_d15, eventout - -58h1h980 pd11 i/oft- fmpi2c1_smba, usart3_cts, quadspi_bk1_io0, sai2_sd_a, fmc_a16, eventout - - 59 g2 l10 81 pd12 i/o ftf - tim4_ch1, fmpi2c1_scl, usart3_rts, quadspi_bk1_io1, sai2_fs_a, fmc_a17, eventout - - 60 g1 k10 82 pd13 i/o ftf - tim4_ch2, fmpi2c1_sda, quadspi_bk1_io3, sai2_sck_a, fmc_a18, eventout - - - - g8 83 vss s - - - - -- -f884 vdd s-- - - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 docid027107 rev 6 53/202 stm32f446xc/e pinout and pin description 66 -61 -k1185 pd14 i/oftf- tim4_ch3, fmpi2c1_scl, sai2_sck_a, fmc_d0, eventout - -62 -k1286 pd15 i/oftf- tim4_ch4, fmpi2c1_sda, fmc_d1, eventout - - - - j12 87 pg2 i/o ft - fmc_a12, eventout - - - - j11 88 pg3 i/o ft - fmc_a13, eventout - -- -j1089 pg4 i/oft- fmc_a14/fmc_ba0, eventout - - - - h12 90 pg5 i/o ft - fmc_a15/fmc_ba1, eventout - -- -h1191 pg6 i/oft- quadspi_bk1_ncs, dcmi_d12, eventout - - - - h10 92 pg7 i/o ft - usart6_ck, fmc_int, dcmi_d13, eventout - -- -g1193 pg8 i/oft- spdifrx_in2, usart6_rts, fmc_sdclk, eventout - - - - - 94 vss s - - - - -- -f10- vdd s-- - - - - e1 c11 95 vddusb s - - - - 37 63 f1 g12 96 pc6 i/o ftf - tim3_ch1, tim8_ch1, fmpi2c1_scl, i2s2_mck, usart6_tx, sdio_d6, dcmi_d0, eventout - 38 64 f2 f12 97 pc7 i/o ftf - tim3_ch2, tim8_ch2, fmpi2c1_sda, spi2_sck/i2s2_ck, i2s3_mck, spdifrx_in1, usart6_rx, sdio_d7, dcmi_d1, eventout - 39 65 f3 f11 98 pc8 i/o ft - traced0, tim3_ch3, tim8_ch3, uart5_rts, usart6_ck, sdio_d0, dcmi_d2, eventout - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 pinout and pin description stm32f446xc/e 54/202 docid027107 rev 6 40 66 d1 e11 99 pc9 i/o ft - mco2, tim3_ch4, tim8_ch4, i2c3_sda, i2s_ckin, uart5_cts, quadspi_bk1_io0, sdio_d1, dcmi_d3, eventout - 41 67 e2 e12 100 pa8 i/o ft - mco1, tim1_ch1, i2c3_scl, usart1_ck, otg_fs_sof, eventout - 42 68 f4 d12 101 pa9 i/o ft - tim1_ch2, i2c3_smba, spi2_sck/i2s2_ck, sai1_sd_b, usart1_tx, dcmi_d0, eventout otg_fs_vbus 43 69 e3 d11 102 pa10 i/o ft - tim1_ch3, usart1_rx, otg_fs_id, dcmi_d1, eventout - 44 70 c1 c12 103 pa11 (1) i/o ft - tim1_ch4, usart1_cts, can1_rx, otg_fs_dm, eventout - 45 71 e4 b12 104 pa12 (1) i/o ft - tim1_etr, usart1_rts, sai2_fs_b, can1_tx, otg_fs_dp, eventout - 46 72 d2 a12 105 pa13(jtms-swdio) i/o ft - jtms-swdio, eventout - - 73 c2 g9 106 vcap_2 s - - - - 47 74 b1 g10 107 vss s - - - - 48 75 a1 f9 108 vdd s - - - - 49 76 c3 a11 109 pa14(jtck-swclk) i/o ft - jtck-swclk, eventout - 50 77 b2 a10 110 pa15(jtdi) i/o ft - jtdi, tim2_ch1/tim2_etr, hdmi_cec, spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, uart4_rts, eventout - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 docid027107 rev 6 55/202 stm32f446xc/e pinout and pin description 66 51 78 d3 b11 111 pc10 i/o ft - spi3_sck/i2s3_ck, usart3_tx, uart4_tx, quadspi_bk1_io1, sdio_d2, dcmi_d8, eventout - 52 79 d4 b10 112 pc11 i/o ft - spi3_miso, usart3_rx, uart4_rx, quadspi_bk2_ncs, sdio_d3, dcmi_d4, eventout - 53 80 a2 c10 113 pc12 i/o ft - i2c2_sda, spi3_mosi/i2s3_sd, usart3_ck, uart5_tx, sdio_ck, dcmi_d9, eventout - -81b3e10114 pd0 i/oft- spi4_miso, spi3_mosi/i2s3_sd, can1_rx, fmc_d2, eventout - -82c4d10115 pd1 i/oft- spi2_nss/i2s2_ws, can1_tx, fmc_d3, eventout - 54 83 d5 e9 116 pd2 i/o ft - tim3_etr, uart5_rx, sdio_cmd, dcmi_d11, eventout - -84 - d9117 pd3 i/oft- traced1, spi2_sck/i2s2_ck, usart2_cts, quadspi_clk, fmc_clk, dcmi_d5, eventout - -85a3c9118 pd4 i/oft- usart2_rts, fmc_noe, eventout - -86 - b9119 pd5 i/oft- usart2_tx, fmc_nwe, eventout - - - - e7 120 vss s - - - - -- -f7121 vdd s-- - - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 pinout and pin description stm32f446xc/e 56/202 docid027107 rev 6 -87b4a8122 pd6 i/oft- spi3_mosi/i2s3_sd, sai1_sd_a, usart2_rx, fmc_nwait, dcmi_d10, eventout - -88a4a9123 pd7 i/oft- usart2_ck, spdifrx_in0, fmc_ne1, eventout - -- -e8124 pg9 i/oft- spdifrx_in3, usart6_rx, quadspi_bk2_io2, sai2_fs_b, fmc_ne2/fmc_nce3, dcmi_vsync, eventout - - - - d8 125 pg10 i/o ft - sai2_sd_b, fmc_ne3, dcmi_d2, eventout - -- -c8126 pg11 i/oft- spi4_sck, spd ifrx_in0, dcmi_d3, eventout - - - - b8 127 pg12 i/o ft - spi4_miso, spdifrx_in1, usart6_rts, fmc_ne4, eventout - - - - d7 128 pg13 i/o ft - traced2, spi4_mosi, usart6_cts, fmc_a24, eventout - - - - c7 129 pg14 i/o ft - traced3, spi4_nss, usart6_tx, quadspi_bk2_io3, fmc_a25, eventout - - - - - 130 vss s - - - - -- -f6131 vdd s-- - - - - - b7 132 pg15 i/o ft - usart6_cts, fmc_sdncas, dcmi_d13, eventout - 55 89 a5 a7 133 pb3(jtdo/traces wo) i/o ft - jtdo/traceswo, tim2_ch2, i2c2_sda, spi1_sck/i2s1_ck, spi3_sck/i2s3_ck, eventout - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 docid027107 rev 6 57/202 stm32f446xc/e pinout and pin description 66 56 90 b5 a6 134 pb4(njtrst) i/o ft - njtrst, tim3_ch1, i2c3_sda, spi1_miso, spi3_miso, spi2_nss/i2s2_ws, eventout - 57 91 a6 b6 135 pb5 i/o ft - tim3_ch2, i2c1_smba, spi1_mosi/i2s1_sd, spi3_mosi/i2s3_sd, can2_rx, otg_hs_ulpi_d7, fmc_sdcke1, dcmi_d10, eventout - 58 92 c5 c6 136 pb6 i/o ft - tim4_ch1, hdmi_cec, i2c1_scl, usart1_tx, can2_tx, quadspi_bk1_ncs, fmc_sdne1, dcmi_d5, eventout - 59 93 b6 d6 137 pb7 i/o ft - tim4_ch2, i2c1_sda, usart1_rx, spdifrx_in0, fmc_nl, dcmi_vsync, eventout - 60 94 a7 d5 138 boot0 i b - - vpp 61 95 c6 c5 139 pb8 i/o ft - tim2_ch1/tim2_etr, tim4_ch3, tim10_ch1, i2c1_scl, can1_rx, sdio_d4, dcmi_d6, eventout - 62 96 c7 b5 140 pb9 i/o ft - tim2_ch2, tim4_ch4, tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, sai1_fs_b, can1_tx, sdio_d5, dcmi_d7, eventout - - 97 - a5 141 pe0 i/o ft - tim4_etr, sai2_mclk_a, fmc_nbl0, dcmi_d2, eventout - - 98 - a4 142 pe1 i/o ft - fmc_nbl1, dcmi_d3, eventout - table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 pinout and pin description stm32f446xc/e 58/202 docid027107 rev 6 63 99 b7 e6 - vss s - - - - - - b8 e5 143 pdr_on s - - - - 64 100 a8 f5 144 vdd s - - - - 1. pa11, pa12, pb14 and pb15 i/os are supplied by vddusb table 10. stm32f446xx pin and ball descriptions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 wlcsp 81 ufbga144 lqfp144 stm32f446xc/e pinout and pin description docid027107 rev 6 59/202 table 11. alternate function port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys port a pa0 - tim2_ch1/ tim2_etr tim5_ch1 tim8_etr - - - usart2_ cts uart4_ tx -- - --- event out pa1 - tim2_ch2 tim5_ch2 - - - - usart2_ rts uart4_ rx quadspi_ bk1_io3 sai2_ mclk_b ---- event out pa2 - tim2_ch3 tim5_ch3 tim9_ch1 - - - usart2_ tx sai2_ sck_b -- - --- event out pa3 - tim2_ch4 tim5_ch4 tim9_ch2 - - sai1_ fs_a usart2_ rx -- otg_hs_ ulpi_d0 ---- event out pa4 - - - - - spi1_nss/i 2s1_ws spi3_nss / i2s3_ws usart2_ ck -- - - otg_hs_ sof dcmi_ hsync - event out pa5 - tim2_ch1/ tim2_etr - tim8_ ch1n - spi1_sck/i 2s1_ck -- - - otg_hs_ ulpi_ck ---- event out pa6 - tim1_ bkin tim3_ch1 tim8_ bkin -spi1_miso i2s2_ mck - - tim13_ch1 - - - dcmi_ pixclk - event out pa7 - tim1_ ch1n tim3_ch2 tim8_ ch1n - spi1_mosi / i2s1_sd - - - tim14_ch1 - - fmc_ sdnwe -- event out pa8 mco1 tim1_ch1 - - i2c3_ scl -- usart1_ ck -- otg_fs_ sof ---- event out pa9 - tim1_ch2 - - i2c3_ smba spi2_sck /i2s2_ck sai1_ sd_b usart1_ tx - - - - - dcmi_d0 - event out pa10 - tim1_ch3 - - - - - usart1_ rx -- otg_fs_ id - - dcmi_d1 - event out pa11 - tim1_ch4 - - - - - usart1_ cts -can1_rx otg_fs_ dm ---- event out pa12 - tim1_etr - - - - - usart1_ rts sai2_ fs_b can1_tx otg_fs_ dp ---- event out pa13 jtms- swdio --------- - - --- event out pa14 jtck- swclk --------- - - --- event out pa15 jtdi tim2_ch1/ tim2_etr -- hdmi_ cec spi1_nss/ i2s1_ws spi3_ nss/ i2s3_ws - uart4_rt s -- - --- event out pinout and pin description stm32f446xc/e 60/202 docid027107 rev 6 port b pb0 - tim1_ch2n tim3_ch3 tim8_ ch2n -- - spi3_mos i/ i2s3_sd uart4_ cts - otg_hs_ ulpi_d1 -sdio_d1- - event out pb1 - tim1_ch3n tim3_ch4 tim8_ ch3n -- - - - - otg_hs_ ulpi_d2 -sdio_d2- - event out pb2 - tim2_ch4 - - - - sai1_ sd_a spi3_mos i/ i2s3_sd - quadspi_ clk otg_hs_ ulpi_d4 - sdio_ck - - event out pb3 jtdo/ traces wo tim2_ch2 - - i2c2_ sda spi1_sck /i2s1_ck spi3_sck / i2s3_ck --- - - --- event out pb4 njtrst - tim3_ch1 - i2c3_ sda spi1_miso spi3_ miso spi2_nss/ i2s2_ws -- - - --- event out pb5 - - tim3_ch2 - i2c1_ smba spi1_mosi /i2s1_sd spi3_ mosi/ i2s3_sd - - can2_rx otg_hs_ ulpi_d7 - fmc_ sdcke1 dcmi_ d10 - event out pb6 - - tim4_ch1 hdmi_ cec i2c1_ scl -- usart1_ tx -can2_tx quadspi_ bk1_ncs - fmc_ sdne1 dcmi_d5 - event out pb7 - - tim4_ch2 - i2c1_ sda -- usart1_ rx spdif_ rx0 -- -fmc_nl dcmi_ vsync - event out pb8 - tim2_ch1/ tim2_etr tim4_ch3 tim10_ ch1 i2c1_ scl - - - - can1_rx - - sdio_d4 dcmi_d6 - event out pb9 - tim2_ ch2 tim4_ch4 tim11_ ch1 i2c1_ sda spi2_nss/ i2s2_ws sai1_ fs_b - - can1_tx - - sdio_d5 dcmi_d7 - event out pb10 - tim2_ch3 - - i2c2_ scl spi2_sck/ i2s2_ck sai1_ sck_a usart3_ tx -- otg_hs_ ulpi_d3 ---- event out pb11 - tim2_ch4 - - i2c2_ sda -- usart3_ rx sai2_ sd_a -- - --- event out pb12 - tim1_bkin - - i2c2_ smba spi2_nss/ i2s2_ws sai1_ sck_b usart3_ ck -can2_rx otg_hs_ ulpi_d5 - otg_ hs_id -- event out pb13 - tim1_ch1n - - - spi2_sck/ i2s2_ck - usart3_ cts -can2_tx otg_hs_ ulpi_d6 ---- event out pb14 - tim1_ch2n - tim8_ ch2n -spi2_miso - usart3_ rts - tim12_ch1 - - otg_ hs_dm -- event out pb15 rtc_ refin tim1_ch3n - tim8_ ch3n - spi2_mosi /i2s2_sd - - - tim12_ch2 - - otg_ hs_dp -- event out table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys stm32f446xc/e pinout and pin description docid027107 rev 6 61/202 port c pc0 - - - - - - sai1_ mclk_b --- otg_hs_ ulpi_stp - fmc_ sdnwe -- event out pc1 - - - - - spi3_mosi /i2s3_sd sai1_ sd_a spi2_mos i /i2s2_sd -- - - --- event out pc2 - - - - - spi2_miso - - - - otg_hs_ ulpi_dir - fmc_ sdne0 -- event out pc3 - - - - - spi2_mosi / i2s2_sd -- - - otg_hs_ ulpi_nxt - fmc_ sdcke0 -- event out pc4 - - - - - i2s1_mck - - spdif_ rx2 -- - fmc_ sdne0 -- event out pc5 - - - - - - - usart3_ rx spdif_ rx3 -- - fmc_ sdcke0 -- event out pc6 - - tim3_ch1 tim8_ch1 fmpi2c1 _scl i2s2_mck - - usart6_t x - - - sdio_d6 dcmi_d0 - event out pc7 - - tim3_ch2 tim8_ch2 fmpi2c1 _sda spi2_sck/ i2s2_ck i2s3_mck spdif_ rx1 usart6_r x - - - sdio_d7 dcmi_d1 - event out pc8 trace d0 - tim3_ch3 tim8_ch3 - - - uart5_ rts usart6_c k - - - sdio_d0 dcmi_d2 - event out pc9 mco2 - tim3_ch4 tim8_ch4 i2c3_ sda i2s_ckin - uart5_ cts - quadspi_ bk1_io0 - - sdio_d1 dcmi_d3 - event out pc10-- - --- spi3_sck / i2s3_ck usart3_ tx uart4_tx quadspi_ bk1_io1 - - sdio_d2 dcmi_d8 - event out pc11-- - --- spi3_ miso usart3_ rx uart4_rx quadspi_ bk2_ncs - - sdio_d3 dcmi_d4 - event out pc12 - - - - i2c2_ sda - spi3_ mosi/ i2s3_sd usart3_ ck uart5_tx - - - sdio_ck dcmi_d9 - event out pc13-- - --- - - - - - - --- event out pc14-- - --- - - - - - - --- event out pc15-- - --- - - - - - - --- event out table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys pinout and pin description stm32f446xc/e 62/202 docid027107 rev 6 port d pd0 - - - - - spi4_miso spi3_ mosi/ i2s3_sd - - can1_rx - - fmc_d2 - - event out pd1 - - - - - - - spi2_nss/ i2s2_ws - can1_tx - - fmc_d3 - - event out pd2 - - tim3_etr - - - - - uart5_rx - - - sdio_cmd dcmi_ d11 - event out pd3 trace d1 ---- spi2_sck/ i2s2_ck - usart2_ cts - quadspi_ clk --fmc_clk dcmi_ d5 - event out pd4 - - - - - - - usart2_ rts -- - -fmc_noe-- event out pd5 - - - - - - - usart2_ tx -- - -fmc_nwe-- event out pd6 - - - - - spi3_ mosi/ i2s3_sd sai1_ sd_a usart2_ rx -- - - fmc_ nwait dcmi_ d10 - event out pd7 - - - - - - - usart2_ ck spdif_ rx0 -- -fmc_ne1-- event out pd8 - - - - - - - usart3_ tx spdif_ rx1 - - - fmc_d13 - - event out pd9 - - - - - - - usart3_ rx - - - - fmc_d14 - - event out pd10-- - --- - usart3_ ck - - - - fmc_d15 - - event out pd11 - --- fmpi2c1 _smba -- usart3_ cts - quadspi_ bk1_io0 sai2_sd_a - fmc_a16 - - event out pd12 - - tim4_ch1 - fmpi2c1 _scl -- usart3_ rts - quadspi_ bk1_io1 sai2_fs_a - fmc_a17 - - event out pd13 - - tim4_ch2 - fmpi2c1 _sda --- - quadspi_ bk1_io3 sai2_sck_a - fmc_a18 - - event out pd14 - - tim4_ch3 - fmpi2c1 _scl --- sai2_ sck_a -- -fmc_d0-- event out pd15 - - tim4_ch4 - fmpi2c1 _sda --- - - - -fmc_d1-- event out table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys stm32f446xc/e pinout and pin description docid027107 rev 6 63/202 port e pe0 - - tim4_etr - - - - - - - sai2_ mclk_a - fmc_ nbl0 dcmi_d2 - event out pe1 - - - - - - - - - - - - fmc_ nbl1 dcmi_d3 - event out pe2 trace clk ----spi4_sck sai1_ mclk_a -- quadspi_ bk1_io2 --fmc_a23-- event out pe3 trace d0 ----- sai1_ sd_b - - - - - fmc_a19 - - event out pe4 trace d1 - - - - spi4_nss sai1_ fs_a - - - - - fmc_a20 dcmi_d4 - event out pe5 trace d2 - - tim9_ch1 - spi4_miso sai1_ sck_a - - - - - fmc_a21 dcmi_d6 - event out pe6 trace d3 - - tim9_ch2 - spi4_mosi sai1_ sd_a - - - - - fmc_a22 dcmi_d7 - event out pe7 - tim1_etr - - - - - - uart5_rx - quadspi_ bk2_io0 -fmc_d4- - event out pe8 - tim1_ch1n - - - - - - uart5_tx - quadspi_ bk2_io1 -fmc_d5- - event out pe9 - tim1_ch1 - - - - - - - - quadspi_ bk2_io2 -fmc_d6- - event out pe10 - tim1_ch2n - - - - - - - - quadspi_ bk2_io3 -fmc_d7- - event out pe11 - tim1_ch2 - - - spi4_nss - - - - sai2_ sd_b - fmc_d8 - - event out pe12 - tim1_ch3n - - - spi4_sck - - - - sai2_ sck_b -fmc_d9- - event out pe13 - tim1_ch3 - - - spi4_miso - - - - sai2_ fs_b - fmc_d10 - - event out pe14 - tim1_ch4 - - - spi4_mosi - - - - sai2_ mclk_b -fmc_d11- - event out pe15 - tim1_bkin - - - - - - - - - - fmc_d12 - - event out table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys pinout and pin description stm32f446xc/e 64/202 docid027107 rev 6 port f pf0 - - - - i2c2_ sda --- - - - -fmc_a0-- event out pf1 - --- i2c2_ scl --- - - - -fmc_a1-- event out pf2 - - - - i2c2_ smba --- - - - -fmc_a2-- event out pf3 - - - - - --- - - - -fmc_a3-- event out pf4 - - - - - --- - - - -fmc_a4-- event out pf5 - - - - - --- - - - -fmc_a5-- event out pf6 - - - tim10_ ch1 -- sai1_ sd_b -- quadspi_ bk1_io3 -- - -- event out pf7 - - - tim11_ ch1 -- sai1_ mclk_b -- quadspi_ bk1_io2 -- - -- event out pf8 - - - - - - sai1_ sck_b - - tim13_ch1 quadspi_ bk1_io0 - - -- event out pf9 - - - - - - sai1_ fs_b - - tim14_ch1 quadspi_ bk1_io1 - - -- event out pf10-- - --- - - - - - - - dcmi_ d11 - event out pf11 - - - - - - - - - - sai2_sd_b - fmc_ sdnras dcmi_ d12 - event out pf12-- - --- - - - - - -fmc_a6-- event out pf13 - - - - fmpi2c1 _smba --- - - - -fmc_a7-- event out pf14 - - - - fmpi2c1 _scl --- - - - -fmc_a8-- event out pf15 - - - - fmpi2c1 _sda --- - - - -fmc_a9-- event out table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys stm32f446xc/e pinout and pin description docid027107 rev 6 65/202 port g pg0 - - - - - - - - - - - - fmc_a10 - - event out pg1 - - - - - - - - - - - - fmc_a11 - - event out pg2 - - - - - - - - - - - - fmc_a12 - - event out pg3 - - - - - - - - - - - - fmc_a13 - - event out pg4 - - - - - - - - - - - - fmc_a14/ fmc_ba0 -- event out pg5 - - - - - - - - - - - - fmc_a15/ fmc_ba1 -- event out pg6 - - - - - - - - - - quadspi_ bk1_ncs -- dcmi_ d12 - event out pg7 - - - - - - - - usart6_c k -- -fmc_int dcmi_ d13 - event out pg8 - - - - - - - spdifrx_ in2 usart6_r ts -- - fmc_ sdclk -- event out pg9 - - - - - - - spdifrx_ in3 usart6_r x quadspi_ bk2_io2 sai2_fs_b - fmc_ne2/ fmc_nce3 dcmi_ vsync (1) - event out pg10 - - - - - - - - - - sai2_sd_b - fmc_ne3 dcmi_d2 - event out pg11-- - --- spi4_ sck spdifrx_ in0 -- - - - dcmi_d3 - event out pg12-- - --- spi4_ miso spdifrx_ in1 usart6_r ts -- -fmc_ne4-- event out pg13 trace d2 ----- spi4_ mosi - usart6_c ts - - - fmc_a24 - - event out pg14 trace d3 ----- spi4_ nss - usart6_t x quadspi_ bk2_io3 --fmc_a25-- event out pg15-- - --- - - usart6_c ts -- - fmc_ sdncas dcmi_ d13 - event out table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys pinout and pin description stm32f446xc/e 66/202 docid027107 rev 6 port h ph0 - - - - - - - - - - - - - - - event out ph1 - - - - - - - - - - - - - - - event out 1. the dcmi_vsync alternate function on pg9 is only available on silicon revision 3. table 11. alternate function (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11/ cec i2c1/2/3 /4/cec spi1/2/3/ 4 spi2/3/4/ sai1 spi2/3/ usart1/ 2/3/uart 5/spdifr x sai/ usart6/ uart4/5/ spdifrx can1/2 tim12/13/ 14/ quadspi sai2/ quadspi/ otg2_hs/ otg1_fs otg1_fs fmc/ sdio/ otg2_fs dcmi - sys docid027107 rev 6 67/202 stm32f446xc/e memory mapping 71 5 memory mapping the memory map is shown in figure 15 figure 15. memory map 0 6 9 0 e \ w h % o r f n & r u w h [ 0 , q w h u q d o s h u l s k h u d o v 0 e \ w h % o r f n ) 0 & 0 e \ w h % o r f n ) 0 & e d q n d q g 4 x d g 6 3 , [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ $ [ & ) ) ) ) ) ) ) [ ' [ ' ) ) ) ) ) ) ) [ ( [ ) ) ) ) ) ) ) ) 6 5 $ 0 . % d o l d v h g % \ e l w e d q g l q j 5 h v h u y h g [ [ % ) ) ) [ & [ ) ) ) ) [ [ ) ) ) ) ) ) ) [ 5 h v h u y h g [ ) ) ) [ [ ) ) ) ) [ 5 h v h u y h g [ & [ ) ) ) ) ) ) ) $ + % [ [ ' ) ) ) ) ) ) ) $ + % 6 5 $ 0 . % d o l d v h g % \ e l w e d q g l q j [ % ) ) [ [ [ ) ) ) ) $ 3 % $ 3 % [ % ) ) [ & [ ) ) ) ) 5 h v h u y h g [ [ ) ) ) ) ) ) ) [ ) ) ) ) $ + % 5 h v h u y h g ) o d v k p h p r u \ [ [ ) ) ) ) ) ) ) [ ) ) ) [ ) ) ) $ ) [ ) ) ) & [ ) ) ) & ) [ [ ) ) ) ) ) [ [ ) ) ) ) ) ) [ [ ) ) ) ) ) 6 \ v w h p p h p r u \ 5 h v h u y h g 5 h v h u y h g $ o l d v h g w r ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q w k h % 2 2 7 s l q v 2 s w l r q % \ w h v 5 h v h u y h g [ ) ) ) & [ ) ) ) ) ) ) ) [ ) ) ) $ [ ) ) ) ) ) ) 5 h v h u y h g [ [ ) ) ) ) 5 h v h u y h g [ [ ) ) ( % ) ) ) [ ) ) ( & [ ) ) ( & ) 2 s w l r q e \ w h v 5 h v h u y h g [ ) ) ( & [ ) ) ( ) ) ) ) [ & r u w h [ 0 l q w h u q d o s h u l s k h u d o v [ ( [ ( ) ) ) ) ) 5 h v h u y h g [ ( [ ) ) ) ) ) ) ) ) 0 e \ w h % o r f n ) 0 & 4 x d g 6 3 , 0 e \ w h % o r f n ) 0 & e d q n 0 e \ w h % o r f n 3 h u l s k h u d o v 0 e \ w h % o r f n 6 5 $ 0 0 e \ w h % o r f n 6 5 $ 0 5 h v h u y h g 5 h v h u y h g memory mapping stm32f446xc/e 68/202 docid027107 rev 6 table 12. stm32f446xc/e register boundary addresses (1) bus boundary address peripheral - 0xe00f ffff - 0xffff ffff reserved cortex-m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals ahb3 0xd000 0000 - 0xdfff ffff fmc bank 6 0xc000 0000 - 0xcfff ffff fmc bank 5 0xa000 2000 - 0x0xbfff ffff reserved 0xa000 1000 - 0x0xa000 1f ff quadspi control register 0xa000 0000 - 0xa000 0fff fmc control register 0x9000 0000 - 0x9fff ffff quadspi 0x8000 0000 - 0x8fff ffff fmc bank 3 0x7000 0000 - 0x0x7fff ffff reserved 0x6000 0000 - 0x6fff ffff fmc bank 1 - 0x5006 0c00- 0x5fff ffff reserved ahb2 0x5006 0800- 0x500f 07ff reserved 0x5005 0400 - 0x5006 07ff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reserved 0x5000 0000 - 0x5003 ffff usb otg fs docid027107 rev 6 69/202 stm32f446xc/e memory mapping 71 - 0x4008 0000- 0x4fff ffff reserved ahb1 0x4004 0000 - 0x4007 ffff usb otg hs 0x4002 bc00- 0x4003 ffff reserved 0x4002 b000 - 0x4002 bbff 0x4002 9400 - 0x4002 afff 0x4002 9000 - 0x4002 93ff 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6800 - 0x4002 7fff 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reserved 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2c00 - 0x4002 2fff reserved 0x4002 2800 - 0x4002 2bff 0x4002 2400 - 0x4002 27ff 0x4002 2000 - 0x4002 23ff 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa table 12. stm32f446xc/e register boundary addresses (1) (continued) bus boundary address peripheral memory mapping stm32f446xc/e 70/202 docid027107 rev 6 - 0x4001 6c00- 0x4001 ffff reserved apb2 0x4001 6800 - 0x4001 6bff 0x4001 5c00 - 0x4001 5fff sai2 0x4001 6000 - 0x4001 67ff reserved 0x4001 5800 - 0x4001 5bff sai1 0x4001 5400 - 0x4001 57ff reserved 0x4001 5000 - 0x4001 53ff 0x4001 4c00 - 0x4001 4fff 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4 0x4001 3000 - 0x4001 33ff spi1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 table 12. stm32f446xc/e register boundary addresses (1) (continued) bus boundary address peripheral docid027107 rev 6 71/202 stm32f446xc/e memory mapping 71 - 0x4000 8000- 0x4000 ffff reserved apb1 0x4000 7c00 - 0x4000 7fff 0x4000 7800 - 0x4000 7bff 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6c00 - 0x4000 6fff hdmi-cec 0x4000 6800 - 0x4000 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff fmpi2c1 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff spdifrx 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff reserved 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 2400 - 0x4000 27ff reserved 0x4000 2000 - 0x4000 23ff tim14 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 0x4000 1400 - 0x4000 17ff tim7 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 1. the grey color is used for reserved boundary addresses. table 12. stm32f446xc/e register boundary addresses (1) (continued) bus boundary address peripheral electrical characteristics stm32f446xc/e 72/202 docid027107 rev 6 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 16 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 17 . figure 16. pin loading conditi ons figure 17. pin input voltage - 3 6 # p & - # 5 p i n - 3 6 - # 5 p i n 6 ) . docid027107 rev 6 73/202 stm32f446xc/e electrical characteristics 175 6.1.6 power supply scheme figure 18. power supply scheme 1. v dda and v ssa must be connected to v dd and v ss , respectively. 2. v ddusb is a dedicated independent usb power supply for the on-chip full-speed otg phy module and associated dp/dm gpios. its value is independent from the v dd and v dda values, but must be the last supply to be provided and the first to disappear. if v dd is different from v ddusb and only one on-chip otg phy is used, the second otg phy gpios (dp/dm) are still supplied at vddusb (3.3v). 3. v ddusb is available only on wlcs p81, ufbga144 and lqfp144 pac kages. for packages where v ddusb pin is not available, it is internally connected to v dd . 4. v cap_2 pad is not available on lqfp64. caution: each power supply pair (v dd /v ss , v dda /v ssa ...) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filterin g capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 0 6 y 9 % d f n x s f l u f x l w u \ 2 6 & . 5 7 & : d n h x s o r j l f % d f n x s u h j l v w h u v e d f n x s 5 $ 0 . h u q h o o r j l f & 3 8 g l j l w d o 5 $ 0 $ q d o r j 5 & v 3 / / 3 r z h u v z l w f k 9 % $ 7 * 3 , 2 v 2 8 7 , 1 ? q ) ? ? ) 9 % $ 7 w r 9 9 r o w d j h u h j x o d w r u 9 ' ' $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) ) o d v k p h p r u \ 9 & $ 3 b 9 & $ 3 b ? ? ) % < 3 $ 6 6 b 5 ( * 3 ' 5 b 2 1 5 h v h w f r q w u r o o h u 9 ' ' 9 6 6 9 ' ' 9 5 ( ) 9 5 ( ) 9 6 6 $ 9 5 ( ) q ) ? ) 2 7 * ) 6 3 + < 9 ' ' 8 6 % q ) ? ) 9 ' ' 8 6 % electrical characteristics stm32f446xc/e 74/202 docid027107 rev 6 6.1.7 current consumption measurement figure 19. current consum ption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 13: voltage characteristics , table 14: current characteristics , and table 15: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. 0 6 y 9 9 % $ 7 9 ' ' 9 ' ' $ , ' ' b 9 % $ 7 , ' ' 9 ' ' 8 6 % table 13. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd, v ddusb and v bat ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on ft & ftf pins (2) 2. v in maximum value must always be respected. refer to table 14 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4.0 input voltage on tta pins v ss ?0.3 4.0 input voltage on any other pin v ss ?0.3 4.0 input voltage on boot0 pin v ss 9.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.15: absolute maximum ratings (electrical sensitivity) - docid027107 rev 6 75/202 stm32f446xc/e electrical characteristics 175 table 14. current characteristics symbol ratings max. unit i vdd total current into sum of all v dd power lines (source) (1) 240 ma i vss total current out of sum of all v ss ground lines (sink) (1) - 240 iv ddusb total current into v ddusb power line (source) 25 i vdd maximum current into each v dd power pin (source) (1) 100 i vss maximum current out of each v ss ground pin (sink) (1) - 100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/os and control pin - 25 i io total output current sunk by sum of all i/os and control pins (2) 120 total output current sunk by sum of all usb i/os 25 total output current sourced by sum of all i/os and control pins (2) -120 i inj(pin) injected current on ft, ftf, rst and b pins ?5/+0 (3) injected current on tta pins 5 (4) i inj(pin) total injected current (sum of all i/o and control pins) (5) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to t he external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the to tal output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. positive injection is not possible on these i/os and d oes not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in >v dda while a negative injection is induced by v in docid027107 rev 6 77/202 stm32f446xc/e electrical characteristics 175 v dd standard operating voltage - 1.7 (2) -3.6 v v dda (3)(4) analog operating voltage (adc limited to 1.2 m samples) must be the same potential as v dd (5) 1.7 (2) -2.4 analog operating voltage (adc limited to 2.4 m samples) 2.4 - 3.6 v bat backup operating voltage - 1.65 - 3.6 vddusb usb supply voltage (supply voltage for pa11,pa12, pb14 and pb15 pins) usb not used 1.7 - 3.6 usb used 3 - 3.6 v 12 regulator on: 1.2 v internal voltage on v cap_1 /v cap_2 pins power scale 3 ((vos[1:0] bits in pwr_cr register = 0x01), 120 mhz hclk max frequency 1.08 1.14 1.20 power scale 2 ((vos[1:0] bits in pwr_cr register = 0x10), 144 mhz hclk max frequency with over-drive off or 168 mhz with over-drive on 1.20 1.26 1.32 power scale 1 ((vos[1:0] bits in pwr_cr register = 0x11), 168 mhz hclk max frequency with over-drive off or 180 mhz with over-drive on 1.26 1.32 1.40 regulator off: 1.2 v external voltage must be supplied from external regulator on v cap_1 /v cap_2 pins (6) max frequency 120 mhz 1.10 1.14 1.20 max frequency 144 mhz 1.20 1.26 1.32 max frequency 168 mhz 1.26 1.32 1.38 v in input voltage on rst, ftf and ft pins (7) 2 v v dd 3.6 v ?0.3 - 5.5 v 1.7 v v dd 2 v ?0.3 - 5.2 input voltage on tta pins - ?0.3 - v dda +0.3 input voltage on boot0 pin - 0 - 9 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (8) lqfp64 - - 345 mw wlcsp81 - - 417 lqfp100 - - 476 lqfp 144 - - 606 ufbga144 (7x7) - - 392 ufbga144(10x10) - - 417 t a ambient temperature for 6 suffix version maximum power dissipation ?40 - 85 c low power dissipation (9) ?40 - 105 ambient temperature for 7 suffix version maximum power dissipation ?40 - 105 c low power dissipation (9) ?40 - 125 t j junction temperature range 6 suffix version ?40 - 105 c 7 suffix version ?40 - 125 table 16. general operating conditions (continued) symbol parameter conditions (1) min typ max unit electrical characteristics stm32f446xc/e 78/202 docid027107 rev 6 6.3.2 vcap_1/vcap_2 external capacitor stabilization for the main regu lator is achieved by connecting external capacitor c ext to the v cap_1 and v cap_2 pin. for packages supporting only 1 v cap pin, the 2 c ext capacitors are replaced by a single capacitor. c ext is specified in table 18 . 1. the over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 v. 2. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). 3. when the adc is used, refer to table 74: adc characteristics . 4. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. 5. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 6. the over-drive mode is not supported when the internal regulator is off. 7. to sustain a voltage higher than vdd+0.3, the inter nal pull-up and pull-down re sistors must be disabled 8. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 9. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 17. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum hclk frequency vs flash memory wait states (1)(2) i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) conversion time up to 1.2 msps 20 mhz (4) 168 mhz with 8 wait states and over-drive off ? no i/o compensation 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 22 mhz 180 mhz with 8 wait states and over-drive on ? no i/o compensation 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 180 mhz with 7 wait states and over-drive on ? i/o compensation works 16-bit erase and program operations v dd = 2.7 to 3.6 v (5) conversion time up to 2.4 msps 30 mhz 180 mhz with 5 wait states and over-drive on ? i/o compensation works 32-bit erase and program operations 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). 4. prefetch is not available. 5. the voltage range for usb full speed phys can drop down to 2. 7 v. however the electrical characteristics of d- and d+ pins will be degraded between 2.7 and 3 v. docid027107 rev 6 79/202 stm32f446xc/e electrical characteristics 175 figure 20. external capacitor c ext 1. legend: esr is the equivalent series resistance. 6.3.3 operating conditi ons at power-up / powe r-down (regulator on) subject to general operating conditions for t a . 6.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . table 18. vcap_1/vcap_ 2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions c ext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 c ext capacitance of external capacitor with a single v cap pin available 4.7 f esr esr of external capacitor with a single v cap pin available < 1 0 6 9 ( 6 5 5 / h d n & table 19. operating conditions at power-up/power-down (regulator on) symbol parameter min max t vdd v dd rise time rate 20 v dd fall time rate 20 table 20. operating conditions at pow er-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20 electrical characteristics stm32f446xc/e 80/202 docid027107 rev 6 6.3.5 reset and power cont rol block characteristics the parameters given in table 21 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 16 . table 21. reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (risi ng edge) 2.54 2.60 2.65 v pls[2:0]=011 (fallin g edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 3.02 v pls[2:0]=110 (risi ng edge) 2.96 3.03 3.10 v pls[2:0]=110 (fallin g edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (fallin g edge) 2.95 3.03 3.09 v v pvdhyst (1) pvd hysteresis - - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 1.68 1.76 v rising edge 1.64 1.72 1.80 v v pdrhyst (1) pdr hysteresis - - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v v borhyst (1) bor hysteresis - - 100 - mv t rsttempo (1)(2) por reset temporization - 0.5 1.5 3.0 ms docid027107 rev 6 81/202 stm32f446xc/e electrical characteristics 175 6.3.6 over-drive switching characteristics when the over-drive mode switches from enabl ed to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. the over-drive switching c haracteristics are given in table 22 . they are sbject to general operating conditions for t a . 6.3.7 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 19: current consumption measurement scheme . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consum ption equivalent to coremark code. i rush (1) inrush current on voltage regulator power- on (por or wakeup from standby) - - 160 200 ma e rush (1) inrush energy on voltage regulator power- on (por or wakeup from standby) v dd = 1.7 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. guaranteed based on test during characterization. 2. the reset temporization is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 21. reset and power control block characteristics (continued) symbol parameter conditions min typ max unit table 22. over-drive switching characteristics (1) 1. guaranteed based on test during characterization. symbol parameter conditions min typ max unit tod_swen over_drive switch enable time hsi - 45 - s hse max for 4 mhz and min for 26 mhz 45 - 100 external hse 50 mhz - 40 - tod_swdis over_drive switch disable time hsi - 20 - hse max for 4 mhz and min for 26 mhz. 20 - 80 external hse 50 mhz - 15 - electrical characteristics stm32f446xc/e 82/202 docid027107 rev 6 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted both to f hclk frequency and v dd range (see table 17: limitations depending on the operating power supply range ). ? regulator on ? the voltage scaling and over-drive mode are adjusted to f hclk frequency as follows: ? scale 3 for f hclk 120 mhz ? scale 2 for 120 mhz < f hclk 144 mhz ? scale 1 for 144 mhz < f hclk 180 mhz. the over-drive is only on at 180 mhz. ? the system clock is hclk, f pclk1 = f hclk /4, and f pclk2 = f hclk /2. ? external clock frequency is 8 mhz and pll is on when f hclk is higher than 16 mhz. ? flash is enabled except if ex plicitly mentioned as disable. ? the maximum values are obtained for v dd = 3.6 v and a maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. docid027107 rev 6 83/202 stm32f446xc/e electrical characteristics 175 table 23. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram (1) symbol parameter conditions f hclk (mhz) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on, all peripherals enabled (3)(4) 180 72 83.0 (5) 100.0 110.0 (5) ma 168 65 71.0 95.3 101.0 150 59 63.6 85.4 100.8 144 (6) 54 58.4 78.8 91.2 120 40 44.9 62.1 73.2 90 30 35.3 50.7 60.0 60 21 25.5 39.2 46.8 30 12 16.2 28.1 36.0 25 10 14.41 26.17 32.4 hsi, pll off, all peripherals enabled 16 6 11.4 23.1 25.2 8 3 9.5 20.3 22.5 4 2.3 8.3 18.9 21.1 2 1.8 7.7 18.1 20.5 external clock, pll on, all peripherals disabled (3) 180 32 42.0 (5) 59.0 75.0 (5) 168 29 35.5 51.4 55.7 150 26 31.5 47.8 51.9 144 (6) 24 29.2 44.7 48.6 120 18 23.3 36.8 40.4 90 14 19.0 31.8 35.1 60 10 14.7 26.9 29.9 30 6 10.7 22.1 24.9 25 5 9.96 21.24 24.02 hsi, pll off, all peripherals disabled (3) 16 3 8.7 18.9 21.9 8 2 8.1 17.8 20.9 4 1.7 7.64 17.23 20.32 2 1.4 7.4 16.94 20.03 1. code and data processing running from sram1 using boot pins. 2. guaranteed based on test during characterization. 3. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 4. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part. 5. tested in production. 6. overdrive off electrical characteristics stm32f446xc/e 84/202 docid027107 rev 6 table 24. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator enable d with prefetch) or ram (1) symbol parameter conditions f hclk (mhz) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock, pll on, all peripherals enabled (3)(4) 180 86 93.0 115.0 125.0 ma 168 (5) 79 85.1 111.2 117.7 150 73 79.6 104.8 111.2 144 (5) 68 73.5 97.3 103.3 120 54 59.3 79.7 84.7 90 42 47.23 65.50 70.10 60 29 33.7 49.5 53.4 30 16 20.8 34.0 37.4 25 13 18.4 31.2 34.5 hsi, pll off, all peripherals enabled (3)(4) 16 8 13.8 25.0 28.3 8 5 10.8 21.1 24.2 4 3.0 9.1 18.9 22.0 2 2.1 8.1 17.8 20.9 external clock, pll on, all peripherals disabled (3) 180 46 55.0 75.0 86.0 168 43 49.6 67.5 72.6 150 41 48.2 65.8 70.8 144 (5) 38 43.6 61.9 66.8 120 32 37.3 53.7 58.0 90 26 30.7 46.0 50.0 60 18 22.8 36.4 40.1 30 10 14.9 27.1 30.2 25 9 13.55 25.40 28.54 hsi, pll off, all peripherals disabled (3) 16 5 11.1 21.8 25.0 8 3 9.5 19.4 22.5 4 2.4 8.34 18.10 21.17 2 1.8 7.77 17.39 20.50 1. code and data processing running from sram1 using boot pins. 2. guaranteed based on test during characterization. 3. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 4. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part. 5. overdrive off docid027107 rev 6 85/202 stm32f446xc/e electrical characteristics 175 table 25. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator disabled) symbol parameter conditions f hclk (mhz) typ max (1) unit ta= 25 c ta=85 c ta=105 c i dd supply current in run mode external clock, pll on, all peripherals enabled (2)(3) 180 81 89.0 110.0 120.0 ma 168 (4) 74 80.2 105.7 112.0 150 69 74.9 99.5 105.6 144 (4) 63 69.3 92.4 98.1 120 51 56.3 76.1 81.1 90 40 45.32 63.19 67.63 60 28 33.1 48.7 52.6 30 16 20.8 34.0 37.4 25 13 18.4 31.2 34.5 external clock, pll on, all peripherals disabled (2)(3) 16 8 13.8 25.0 28.2 8 5 10.8 21.1 24.2 4 3.0 9.1 19.0 22.0 2 2.1 8.1 17.9 20.9 180 41 47.0 69.0 79.0 168 38 43.2 61.9 67.1 150 37 41.8 60.3 65.4 144 (4) 34 39.3 56.9 61.6 120 29 34.3 50.2 54.4 hsi, pll off, all peripherals disabled (3) 90 24 28.8 43.6 47.5 60 17 22.0 35.6 39.2 30 10 14.8 27.0 30.1 25 8 13.51 25.36 28.47 hsi, pll off, all peripherals disabled (3) 16 5 11.1 21.8 24.9 8 3 9.5 19.4 22.5 4 2.3 8.35 18.12 21.17 2 1.8 7.78 17.42 20.51 1. guaranteed based on test during charac terization unless otherwise specified. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 register ), add an additional power consumption of 1.6 ma per adc for the analog part. 4. overdrive off electrical characteristics stm32f446xc/e 86/202 docid027107 rev 6 table 26. typical and maximum current consumption in sleep mode (1) symbol parameter conditions fhclk (mhz) typ max unit t a = 25 c t a = 25 c t a = 25 c idd supply current in sleep mode all peripherals enabled external clock, pll on, flash on 180 51.2 59.00 77.25 102.00 ma 168 (2) 46.8 53.94 66.48 79.40 150 42.2 49.26 60.84 73.41 144 (2) 38.6 45.37 55.47 66.96 120 29.3 35.70 42.49 51.46 90 22.8 29.17 34.78 43.12 60 16.3 22.41 27.12 34.83 30 10.1 16.03 19.72 26.86 25 9.0 14.92 18.41 25.38 hsi, pll off, flash on 16 6.5 13.10 15.1 22.3 8 5.2 12.31 13.5 20.4 4 4.5 11.63 12.5 19.3 2 4.1 11.23 12.0 18.8 docid027107 rev 6 87/202 stm32f446xc/e electrical characteristics 175 idd supply current in sleep mode external clock, pll on all peripherals disabled flash on 180 11.36 17.59 28.2 51.6 ma 168 (2) 10.20 16.19 22.0 31.8 150 9.53 15.59 21.1 30.9 144 (2) 8.90 14.87 19.7 28.4 120 7.35 13.24 16.5 23.3 90 6.39 12.40 15.3 21.9 60 5.28 11.17 14.1 20.7 30 4.43 10.31 13.1 19.6 25 4.23 10.12 12.85 19.30 flash in deep power down mode 180 8.3 13.44 30.72 37.20 168 (2) 7.3 12.25 25.16 28.80 150 6.7 11.60 24.27 27.84 144 (2) 6.1 11.08 23.25 26.28 120 4.7 9.64 20.95 23.72 90 3.8 8.80 19.77 22.57 60 2.8 7.74 18.69 21.32 30 2.0 6.89 17.66 20.40 25 1.8 6.70 17.43 20.17 flash in stop mode 180 8.3 13.44 30.72 37.20 168 (2) 7.3 12.25 25.16 28.80 150 6.7 11.60 24.27 27.84 144 (2) 6.1 11.08 23.25 26.28 120 4.7 9.64 20.95 23.72 90 3.8 8.80 19.77 22.57 60 2.8 7.74 18.69 21.32 30 2.0 6.89 17.66 20.40 25 1.8 6.70 17.43 20.17 table 26. typical and maximum current consumption in sleep mode (1) (continued) symbol parameter conditions fhclk (mhz) typ max unit t a = 25 c t a = 25 c t a = 25 c electrical characteristics stm32f446xc/e 88/202 docid027107 rev 6 idd supply current in sleep mode hsi, pll off, all peripherals disabled flash on 16 3.89 4.93 11.72 18.54 ma 8 2.45 3.29 11.66 18.46 4 1.69 2.56 11.60 18.40 2 1.28 2.22 11.57 18.37 flash in deep power down mode 16 1.0 6.65 16.54 19.50 8 0.9 6.93 16.48 19.45 4 0.9 6.90 16.43 19.39 2 0.9 6.88 16.41 19.37 flash in stop mode 16 1.0 6.7 16.5 19.5 8 0.9 6.9 16.5 19.5 4 0.9 6.9 16.4 19.4 2 0.9 6.9 16.4 19.4 1. guaranteed based on test during charac terization unless otherwise specified. 2. overdrive off table 26. typical and maximum current consumption in sleep mode (1) (continued) symbol parameter conditions fhclk (mhz) typ max unit t a = 25 c t a = 25 c t a = 25 c docid027107 rev 6 89/202 stm32f446xc/e electrical characteristics 175 table 27. typical and maximum current consumptions in stop mode symbol parameter conditions typ max unit v dd = 3.6 v t a = 25 c t a = 25 c (1) t a = 85 c t a = 105 c (1) i dd_stop_nm (normal mode) supply current in stop mode with voltage regulator in main regulator mode flash memory in stop mode, all oscillators off, no independent watchdog 0.234 1.2 10 16 ma flash memory in deep power down mode, all oscillators off, no independent watchdog 0.205 1 9.5 15 supply current in stop mode with voltage regulator in low power regulator mode flash memory in stop mode, all oscillators off, no independent watchdog 0.15 0.95 8.5 14 flash memory in deep power down mode, all oscillators off, no independent watchdog 0.121 0.9 6 12 i dd_stop_ud m (under- drive mode) supply current in stop mode with voltage regulator in main regulator and under-drive mode flash memory in deep power down mode, main regulator in under-drive mode, all oscillators off, no independent watchdog 0.119 0.4 3 5 supply current in stop mode with voltage regulator in low power regulator and under-drive mode flash memory in deep power down mode, low power regulator in under-drive mode, all oscillators off, no independent watchdog 0.055 0.35 3 5 1. data based on characteriza tion, tested in production. electrical characteristics stm32f446xc/e 90/202 docid027107 rev 6 table 28. typical and maximum current consumptions in standby mode symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c v dd = 1.7 v v dd = 2.4 v v dd = 3.3 v v dd = 3.3 v i dd_stby supply current in standby mode backup sram on, and lse oscillator in low power mode 2.43 3.44 4.12 7 20 36 a backup sram off, rtc on and lse oscillator in low power mode 1.81 2.81 3.33 6 17 31 backup sram on, rtc on and lse oscillator in high drive mode 3.32 4.33 4.95 8 21 37 backup sram off, rtc on and lse oscillator in high drive mode 2.57 3.59 4.16 7 18 32 backup sram on, rtc and lse off 2.03 2.73 3.5 6 (3) 19 35 (3) backup sram off, rtc and lse off 1.28 1.97 2.03 5 (3) 16 30 (3) 1. when the pdr is off (internal reset is off), the typical current consumption is reduced by 1.2 a. 2. guaranteed based on test during characte rization unless otherwise specified. 3. tested in production. docid027107 rev 6 91/202 stm32f446xc/e electrical characteristics 175 figure 21. typical v bat current consumption (rtc on/backup ram off and lse in low power mode) table 29. typical and maximum current consumptions in v bat mode symbol parameter conditions (1) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat backup domain supply current backup sram on, rtc on and lse oscillator in low power mode 1.46 1.62 1.83 6 11 a backup sram off, rtc on and lse oscillator in low power mode 0.72 0.85 1.00 3 5 backup sram on, rtc on and lse oscillator in high drive mode 2.24 2.40 2.64 - - backup sram off, rtc on and lse oscillator in high drive mode 1.50 1.64 1.86 - - backup sram on, rtc and lse off 0.74 0.75 0.78 5 10 backup sram off, rtc and lse off 0.05 0.05 0.05 2 4 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. guaranteed based on test during characterization. electrical characteristics stm32f446xc/e 92/202 docid027107 rev 6 figure 22. typical v bat current consumption (rtc on/backup ram off and lse in high drive mode) additional current consumption the mcu is placed under the following conditions: ? all i/o pins are configured in analog mode. ? the flash memory access time is adjusted to fhclk frequency. ? the voltage scaling is adjusted to fhclk frequency as follows: ? scale 3 for f hclk 120 mhz, ? scale 2 for 120 mhz < f hclk 144 mhz ? scale 1 for 144 mhz < f hclk 180 mhz. the over-drive is only on at 180 mhz. ? the system clock is hclk, f pclk1 = f hclk /4, and f pclk2 = f hclk /2. ? hse crystal clock frequency is 8 mhz. ? flash is enabled except if exp licitly mentioned as disable. ? when the regulator is off, v12 is provided externally as described in table 16: general operating conditions ? t a = 25 c. docid027107 rev 6 93/202 stm32f446xc/e electrical characteristics 175 table 30. typical current consumption in run mode, code with data processing running from flash memory or ram, regulator on (art accelerator enabled except prefetch), vdd=1.7 v (1) symbol parameter conditions f hclk (mhz) typ max unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode from v dd supply all peripherals enabled 168 65.11 70.0 79.7 90.0 ma 150 58.31 62.8 73.4 79.9 144 53.14 57.1 69.9 75.3 120 39.58 47.2 60.7 71.4 90 29.99 34.70 45.23 49.34 60 20.37 25.2 35.2 38.2 30 11.37 12.9 28.4 33.2 25 9.65 10.9 17.8 24.3 all peripherals disabled 168 29.74 32.43 42.4 48.5 150 25.81 29.12 39.4 43.8 144 24.57 26.61 36.0 41.9 120 17.69 22.09 32.9 40.8 90 13.58 15.92 30.0 36.5 60 9.41 11.05 24.4 30.2 30 5.44 6.64 15.0 22.0 25 4.73 5.72 12.57 19.06 1. when peripherals are enabled, the power consumption correspon ding to the analog part of the peripherals (such as adc, or dac) is not included. electrical characteristics stm32f446xc/e 94/202 docid027107 rev 6 table 31. typical current consumption in r un mode, code with data processing running from flash memory, regulator off (art accelerator enabled except prefetch) (1) symbol parameter conditions f hclk (mhz) vdd=3.3 v vdd=1.7 v unit i dd12 i dd i dd12 i dd i dd12 / i dd supply current in run mode from v 12 and v dd supply all peripherals enabled 168 61.72 1.6 60.15 1.5 ma 150 51.69 1.5 55.46 1.4 144 51.45 1.5 50.94 1.3 120 38.94 1.3 40.66 1.2 90 29.48 1.1 28.18 1.0 60 19.23 1.0 20.05 0.8 30 10.41 0.9 11.26 0.7 25 8.83 0.8 9.56 0.6 all peripherals disabled 168 31.44 1.6 30.06 1.5 150 28.67 1.5 27.38 1.4 144 25.51 1.5 23.37 1.3 120 19.06 1.3 21.73 1.2 90 14.83 1.2 14.74 1.0 60 10.16 1.0 10.30 0.8 30 5.41 0.9 5.64 0.7 25 4.599 0.8 4.80 0.6 1. when peripherals are enabled, the power consumption correspon ding to the analog part of the peripherals (such as adc, or dac) is not included. docid027107 rev 6 95/202 stm32f446xc/e electrical characteristics 175 table 32. typical current consumption in sleep mode, regulator on, v dd =1.7 v (1) symbol parameter conditions f hclk (mhz) typ max unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode from v dd supply all peripherals enabled flash on 168 43.7 47.5 66.5 79.3 ma 150 39.2 42.7 60.7 73.3 144 35.7 38.8 55.3 66.9 120 26.5 28.6 41.8 51.6 90 20.0 21.91 33.85 43.20 60 13.6 15.2 25.8 34.9 30 7.4 8.5 18.4 27.0 25 6.3 7.5 16.9 25.5 all peripherals disabled, flash on 168 7.3 8.6 21.2 31.9 150 6.6 7.94 20.4 31.0 144 6.0 7.3 18.6 28.5 120 4.6 5.5 14.9 23.4 90 3.6 4.6 13.6 22.1 60 2.6 3.4 12.5 20.8 30 1.8 2.7 11.3 19.7 25 1.6 2.49 11.09 19.42 1. when peripherals are enabled, the power consumption correspon ding to the analog part of the peripherals (such as adc, or dac) is not included. electrical characteristics stm32f446xc/e 96/202 docid027107 rev 6 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 56: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. table 33. typical current consumption in sleep mode, regulator off (1) symbol parameter conditions f hclk (mhz) vdd=3.3 v vdd=1.7 v unit i dd12 i dd i dd12 i dd - i dd12 /i dd supply current in sleep mode from v 12 and v dd supply all peripherals enabled 180 47.605 1.2 na na ma 168 44.35 1.0 41.53 0.8 150 40.58 0.9 39.96 0.8 144 35.68 0.9 34.60 0.7 120 27.30 0.9 29.11 0.7 90 20.69 0.8 19.78 0.6 60 13.88 0.7 13.36 0.6 30 7.66 0.7 7.85 0.6 25 6.49 0.7 6.66 0.5 all peripherals disabled 180 8.71 1.2 na na 168 7.00 0.9 8.42 0.8 150 6.88 0.9 7.61 0.8 144 6.29 0.9 6.99 0.7 120 4.87 0.9 5.95 0.7 90 3.78 0.8 3.96 0.6 60 2.66 0.7 2.80 0.6 30 1.65 0.7 1.74 0.6 25 1.45 0.7 1.52 0.5 1. when peripherals are enabled, the power c onsumption corresponding to the analog part of the peripherals (such as adc, or dac) is not included. docid027107 rev 6 97/202 stm32f446xc/e electrical characteristics 175 caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 35: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current f rom the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: i sw v dd f sw c = where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. table 34. switching output i/o current consumption (1) symbol parameter conditions i/o toggling frequency (fsw) typ unit i ddio i/o switching current v dd = 3.3 v c= c int (2) 2 mhz 0.0 ma 8 mhz 0.2 25 mhz 0.6 50 mhz 1.1 60 mhz 1.3 84 mhz 1.8 90 mhz 1.9 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.1 8 mhz 0.4 25 mhz 1.23 50 mhz 2.43 60 mhz 2.93 84 mhz 3.86 90 mhz 4.07 electrical characteristics stm32f446xc/e 98/202 docid027107 rev 6 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? hclk is the system clock. f pclk1 = f hclk /4, and f pclk2 = f hclk /2. the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ?f hclk = 180 mhz (scale1 + over-drive on), f hclk = 144 mhz (scale 2), f hclk = 120 mhz (scale 3)" ? ambient operating temperature is 25 c and v dd =3.3 v. i ddio i/o switching current v dd = 3.3 v c ext = 10 pf c = c int + c ext + c s 2 mhz 0.18 ma 8 mhz 0.67 25 mhz 2.09 50 mhz 3.6 60 mhz 4.5 84 mhz 7.8 90 mhz 9.8 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.26 8 mhz 1.01 25 mhz 3.14 50 mhz 6.39 60 mhz 10.68 v dd = 3.3 v c ext = 33 pf c = c int + cext + c s 2 mhz 0.33 8 mhz 1.29 25 mhz 4.23 50 mhz 11.02 1. c s is the pcb board capacitance including the pad pin. c s = 7 pf (estimated value). 2. this test is performed by cutting the lqfp144 package pin (pad removal). table 34. switching output i/o current consumption (1) (continued) symbol parameter conditions i/o toggling frequency (fsw) typ unit docid027107 rev 6 99/202 stm32f446xc/e electrical characteristics 175 table 35. peripheral current consumption peripheral i dd (typ appli) unit scale 1 + overdrive scale 2 scale 3 ahb1 gpioa 2.29 2.14 1.89 a/mhz gpiob 2.29 2.13 1.89 gpioc 2.33 2.17 1.93 gpiod 2.34 2.19 1.94 gpioe 2.39 2.19 1.93 gpiof 2.31 2.14 1.91 gpiog 2.36 2.19 1.94 gpioh 2.13 1.98 1.75 crc 0.53 0.51 0.46 bkpsram 0.76 0.72 0.65 dma1 (1) 2.39n + 4.13 2.23n+3.56 1.97n+3.51 dma2 (1) 2.39n + 4.45 2.19n+3.72 2.00n+3.66 otg_hs+ulpi 45.45 42.08 37.28 ahb2 dcmi 3.74 3.42 3.01 a/mhz otgfs 30.04 27.88 24.69 ahb3 fmc 16.15 15.01 13.33 a/mhz qspi 16.78 15.60 13.84 electrical characteristics stm32f446xc/e 100/202 docid027107 rev 6 apb1 tim2 18.18 16.92 15.07 a/mhz tim3 14.49 13.47 12.00 tim4 15.18 14.11 12.50 tim5 16.91 15.69 14.07 tim6 2.69 2.47 2.20 tim7 2.56 2.44 2.17 tim12 7.07 6.56 5.83 tim13 4.96 4.64 4.07 tim14 5.09 4.72 4.27 wwdg 1.07 1.00 0.93 spi2 (2) 1.89 1.78 1.57 spi3 (2) 1.93 1.81 1.67 spdifrx 6.91 6.44 5.80 usart2 4.20 3.83 3.40 usart3 4.22 3.94 3.50 uart4 4.13 3.89 3.40 uart5 4.04 3.78 3.33 i2c1 3.98 3.69 3.33 i2c2 3.91 3.61 3.17 i2c3 3.76 3.53 3.13 fmpi2c1 5.51 5.19 4.57 can1 6.58 6.14 5.43 can2 5.91 5.56 4.90 cec 0.71 0.69 0.60 dac 2.96 2.72 2.40 table 35. peripheral current consumption (continued) peripheral i dd (typ appli) unit scale 1 + overdrive scale 2 scale 3 docid027107 rev 6 101/202 stm32f446xc/e electrical characteristics 175 6.3.8 wakeup time from low-power modes the wakeup times given in table 36 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd =3.3 v. apb2 tim1 17.51 16.28 14.43 a/mhz tim8 18.40 17.10 15.22 usart1 4.53 4.21 3.72 usart6 4.53 4.21 3.72 adc1 4.69 4.35 3.85 adc2 4.70 4.35 3.87 adc3 4.66 4.31 3.82 sdio 9.06 8.38 7.47 spi1 1.97 1.89 1.67 spi4 1.88 1.75 1.57 syscfg 1.51 1.40 1.23 tim9 8.17 7.64 6.77 tim10 5.07 4.75 4.22 tim11 5.37 5.06 4.50 sai1 3.89 3.64 3.17 sai2 3.74 3.49 3.10 bus matrix 8.15 8.10 7.13 1. n = number of strean enable (1..8) 2. to enable an i2s peripheral, first set the i2smod bit and then the i2se bit in the spi_i2scfgr register. table 35. peripheral current consumption (continued) peripheral i dd (typ appli) unit scale 1 + overdrive scale 2 scale 3 electrical characteristics stm32f446xc/e 102/202 docid027107 rev 6 6.3.9 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 56: i/o static characteristics . however, the recommended clock input waveform is shown in figure 23 . the characteristics given in table 37 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 16 . table 36. low-power mode wakeup timings symbol parameter conditions typ (1) max (1) unit t wusleep (2) wakeup from sleep - 6 6 cpu clock cycle t wusleepfdsm (1) wakeup from sleep with flash memory in deep power down mode - 33.5 50 s t wustop (2) wakeup from stop mode with mr/lp regulator in normal mode main regulator is on 12.8 15 main regulator is on and flash memory in deep power down mode 104.9 115 low power regulator is on 20.6 28 low power regulator is on and flash memory in deep power down mode 112.8 120 t wustop (2) wakeup from stop mode with mr/lp regulator in under-drive mode main regulator in under-drive mode (flash memory in deep power- down mode) 110 140 low power regulator in under-drive mode (flash memory in deep power- down mode) 114.4 128 t wustdby (2)(3) wakeup from standby mode - 325 400 1. guaranteed based on test during characterization. 2. the wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. t wustdby maximum value is given at ?40 c. docid027107 rev 6 103/202 stm32f446xc/e electrical characteristics 175 low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard i/o. the external clock signal has to respect the table 56: i/o static characteristics . however, the recommended clock input waveform is shown in figure 24 . the characteristics given in table 38 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 16 . table 37. high-speed external user clock characteristics symbol parameter condit ions min typ max unit f hse_ext external user clock source frequency (1) - 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) --5-pf ducy (hse) duty cycle - 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 38. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) - - 200 c in(lse) osc32_in input capacitance (1) --5-pf ducy (lse) duty cycle - 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design. electrical characteristics stm32f446xc/e 104/202 docid027107 rev 6 figure 23. high-speed external clock source ac timing diagram figure 24. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 39 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). a i / 3 # ? ) . % x t e r n a l 3 4 - & c l o c k s o u r c e 6 ( 3 % ( t f ( 3 % t 7 ( 3 % ) , 4 ( 3 % t t r ( 3 % t 7 ( 3 % f ( 3 % ? e x t 6 ( 3 % , d l 2 6 & b , 1 ( [ w h u q d o 6 7 0 ) f o r f n v r x u f h 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / docid027107 rev 6 105/202 stm32f446xc/e electrical characteristics 175 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-freque ncy applications, and selected to match the requirements of the crystal or resonator (see figure 25 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 25. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 40 . in the application, the resonator and the load capacitors have to be placed as close as table 39. hse 4-26 mhz oscillator characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit f osc_in oscillator frequency - 4 - 26 mhz r f feedback resistor - - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz - 450 - a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz - 530 - acc hse (2) 2. this parameter depends on the crystal used in the application. the minimum and maximum values must be respected to comply with usb standard specifications. hse accuracy - -500 - 500 ppm g m _crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is guaranteed based on test during ch aracterization. it is measured for a standard crystal resonator and it can vary si gnificantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms d l 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( & / 5 ) 6 7 0 ) 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q 5 ( ; 7 & / electrical characteristics stm32f446xc/e 106/202 docid027107 rev 6 possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 26. typical applicati on with a 32.768 khz crystal table 40. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design. symbol parameter conditions min typ max unit r f feedback resistor - - 18.4 - m i dd lse current consumption - - - 1 a acc lse (2) 2. this parameter depends on the crystal used in t he application. refer to application note an2867. lse accuracy - -500 - 500 ppm g m _crit_max maximum critical crystal g m startup low-power mode - - 0.56 a/v startup high-drive mode - - 1.5 t su(lse) (3) 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is guaranteed based on test during characterization. it is measured for a standard crystal resonator and it can va ry significantly with t he crystal manufacturer. startup time v dd is stabilized - 2 - s d l 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / 5 ) 6 7 0 ) n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q & / docid027107 rev 6 107/202 stm32f446xc/e electrical characteristics 175 6.3.10 internal clock source characteristics the parameters given in table 41 and table 42 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 16 . high-speed internal (hsi) rc oscillator figure 27. lacc hsi versus temperature 1. guaranteed based on test during characterization. table 41. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. guaranteed by design. --1% t a = - 40 to 105 c (3) 3. guaranteed based on test during characterization. - 8 - 4.5 % t a = - 10 to 85 c (3) - 4 - 4 % t a = 25 c (4) 4. factory calibrated, parts not soldered. - 1 - 1 % t su(hsi) (2) hsi oscillator startup time --2.24s i dd(hsi) (2) hsi oscillator power consumption - - 60 80 a - 3 6 - i n - a x 4 y p i c a l 4 ! ? # ! # # ( 3 ) electrical characteristics stm32f446xc/e 108/202 docid027107 rev 6 low-speed internal (lsi) rc oscillator figure 28. acc lsi versus temperature 6.3.11 pll characteristics the parameters given in table 43 and table 44 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 16 . table 42. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed based on test during characterization.. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a - 3 6 . o r m a l i z e d d e v i a t i o n 4 e m p e r a t u r e ? # m a x a v g m i n table 43. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) -0.95 (2) 12.10mhz f pll_out pll multiplier output clock - 12.5 - 180 mhz f pll48_out 48 mhz pll multiplier output clock - - 48 75 mhz f vco_out pll vco output - 100 - 432 mhz docid027107 rev 6 109/202 stm32f446xc/e electrical characteristics 175 t lock pll lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples -330 - i dd(pll) (4) pll power consumption on vdd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. guaranteed based on test during characterization. table 43. main pll characteristics (continued) symbol parameter conditions min typ max unit table 44. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) -0.95 (2) 12.10mhz f plli2s_out plli2s multiplier output clock - - - 216 mhz f vco_out plli2s vco output - 100 - 432 mhz t lock plli2s lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps electrical characteristics stm32f446xc/e 110/202 docid027107 rev 6 6.3.12 pll spread spec trum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 52: emi characteristics ). it is available only on the main pll. i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed based on test during characterization. table 44. plli2s (audio pll) characteristics (continued) symbol parameter conditions min typ max unit table 45. pllisai characteristics symbol parameter conditions min typ max unit f pllsai_in pllsai input clock (1) -0.95 (2) 12.10mhz f pllsai_out pllsai multiplier ou tput clock - - - 216 mhz f vco_out pllsai vco output - 100 - 432 mhz t lock pllsai lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) main sai clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps fs clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(pllsai) (4) pllsai power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pllsai) (4) pllsai power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed based on test during characterization. docid027107 rev 6 111/202 stm32f446xc/e electrical characteristics 175 equation 1 the frequency modulation period (modeper) is given by the equation below: modeper round f pll_in 4f mod () ? [] = f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation depth (modeper) is given by e quation 1: modeper round 10 6 410 3 () ? [] 250 == equation 2 equation 2 allows to calculate the increment step (incs tep): incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = f vco_out must be expressed in mhz. with a modulation depth (md) = s2 % (4 % peak to peak), and plln = 240 (in mhz): incstep round 2 15 1 ? () 2240 () 100 5 250 () ? [] 126md(quantitazed)% == an amplitude quantization error may be generat e d because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = as a result: md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) == table 46. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - - 2 15 ? 1- 1. guaranteed by design. electrical characteristics stm32f446xc/e 112/202 docid027107 rev 6 figure 29 and figure 30 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 29. pll output clock waveforms in center spread mode figure 30. pll output clock waveforms in down spread mode 6.3.13 memory characteristics flash memory the characteristics are given at ta = - 40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e x t m o d e m d a i m d ) u h t x h q f \ 3 / / b 2 8 7 7 l p h ) w p r g h [ w p r g h [ p g d l e table 47. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v - 5 - ma write / erase 16-bit mode, v dd = 2.1 v - 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - docid027107 rev 6 113/202 stm32f446xc/e electrical characteristics 175 table 48. flash memory programming symbol parameter conditions min (1) typ max (1) 1. guaranteed based on test during characterization. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) 2. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -816 s program/erase parallelism (psize) = x 16 -5.511 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.7 - 3.6 v table 49. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 3.5 - s v prog programming voltage - 2.7 - 3.6 v electrical characteristics stm32f446xc/e 114/202 docid027107 rev 6 6.3.14 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 51 . they are based on the ems levels and classes defined in application note an1709. v pp v pp voltage range - 7 - 9 v i pp minimum current sunk on the v pp pin -10--ma t vpp (3) cumulative time during which v pp is applied - - - 1 hour 1. guaranteed by design. 2. the maximum programming time is measured after 100k erase operations. 3. v pp should only be connected during programming/erasing. table 50. flash memory endurance and data retention symbol parameter conditions value unit -- min (1) 1. guaranteed based on test during characterization. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 49. flash memory programming with v pp (continued) symbol parameter conditions min (1) typ max (1) unit docid027107 rev 6 115/202 stm32f446xc/e electrical characteristics 175 designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. table 51. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 4b electrical characteristics stm32f446xc/e 116/202 docid027107 rev 6 6.3.15 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin table 52. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 8/180 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp144 package, conforming to sae j1752/3 eembc, art on, all peripheral clocks enabled, clock dithering disabled. 0.1 to 30 mhz 11 dbv 30 to 130 mhz 10 130 mhz to 1ghz 11 sae emi level 3 - v dd = 3.3 v, t a = 25 c, lqfp144 package, conforming to sae j1752/3 eembc, art on, all peripheral clocks enabled, clock dithering enabled 0.1 to 30 mhz 24 dbv 30 to 130 mhz 25 130 mhz to 1ghz 20 sae emi level 4 - table 53. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = + 25 c conforming to ansi/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = + 25 c conforming to ansi/esd stm5.3.1, lqfp64, lqfp100, wlcsp81 packages c4 500 t a = + 25 c conforming to ansi/esd stm5.3.1, lqfp144, ufbga144 (7 x 7), ufbga144 (10 x 10) packages c3 250 1. guaranteed based on test during characterization. docid027107 rev 6 117/202 stm32f446xc/e electrical characteristics 175 these tests are compliant with eia/jesd 78a ic latchup standard. 6.3.16 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induc ed leakage current on adjacent pins (out of ? 5 a/+0 a range), or other functi onal failure (for example reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 55 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 54. electric al sensitivities symbol parameter c onditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 55. i/o current in jection susceptibility (1) symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin ?0 na ma injected current on nrst pin ?0 na injected current on pe2, pe3, pe4, pe5, pe6, pc13, pc14, pf10, ph0, ph1, nrst, pc0, pc1, pc2, pc3, pg15, pb3, pb4, pb5, pb6, pb7, pb8, pb9, pe0, pe1 ?0 na injected current on any other ft and ftf pins -5 na injected current on any other pins ?5 +5 1. na = not applicable . electrical characteristics stm32f446xc/e 118/202 docid027107 rev 6 6.3.17 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 56: i/o static characteristics are derived from tests performed under the conditions summarized in table 16 . all i/os are cmos and ttl compliant. table 56. i/o static characteristics symbol parameter conditions min typ max unit v il ft, ftf, tta and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.35v dd ?0.04 (1) v 0.3v dd (2) boot0 i/o input low level voltage 1.75 v v dd 3.6 v, ? 40 c t a 105 c -- 0.1v dd +0.1 (1) 1.7 v v dd 3.6 v, 0 c t a 105 c -- v ih ft, ftf, tta and nrst i/o input high level voltage (4) 1.7 v v dd 3.6 v 0.45v dd +0.3 (1) -- v 0.7v dd (2) boot0 i/o input high level voltage 1.75 v v dd 3.6 v, ? 40 c t a 105 c 0.17v dd +0.7 (1) -- 1.7 v v dd 3.6 v, 0 c t a 105 c v hys ft, ftf, tta and nrst i/o input hysteresis 1.7 v v dd 3.6 v - 10%v dd - v boot0 i/o input hysteresis 1.75 v v dd 3.6 v, ?40 c t a 105 c - 100m - 1.7 v v dd 3.6 v, 0 c t a 105 c -- i lkg i/o input leakage current (3) v ss v in v dd -- 1 a i/o ft input leakage current (4) v in = 5 v - - 3 docid027107 rev 6 119/202 stm32f446xc/e electrical characteristics 175 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 31 . r pu weak pull-up equivalent resistor (5) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v ss 30 40 50 k pa10/pb12 (otg_fs_id, otg_hs_id) 71014 r pd weak pull- down equivalent resistor (6) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v dd 30 40 50 pa10/pb12 (otg_fs_id, otg_hs_id) 71014 c io (7) i/o pin capacitance - - 5 - pf 1. guaranteed by design. 2. tested in production. 3. leakage could be higher than the maximum value, if negat ive current is injected on adjacent pins, refer to table 55: i/o current injection susceptibility 4. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors must be disabled. leakage could be higher than the maximum value, if negative cu rrent is injected on adjacent pins.refer to table 55: i/o current injection susceptibility 5. pull-up resistors are designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance is minimum (~10% order). 6. pull-down resistors are designed with a true resistance in seri es with a switchable nmos. this nmos contribution to the series resistance is minimum (~10% order). 7. hysteresis voltage between schmitt trigger switch ing levels. guaranteed based on te st during characterization. table 56. i/o static characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f446xc/e 120/202 docid027107 rev 6 figure 31. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 14 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 14 ). output voltage levels unless otherwise specified, the parameters given in table 57 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 16 . all i/os are cmos and ttl compliant. 0 6 9 9 ' ' 9 9 , / 9 , + 9 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , / p d [ 9 ' ' % d v h g r q ' h v l j q v l p x o d w l r q v 9 , / p d [ 9 ' ' 7 7 / u h t x l u h p h q w 9 , + p l q 9 7 7 / u h t x l u h p h q w 9 , / p d [ 9 $ u h d q r w g h w h u p l q h g % d v h g r q ' h v l j q v l p x o d w l r q v 9 , + p l q 9 ' ' docid027107 rev 6 121/202 stm32f446xc/e electrical characteristics 175 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 32 and table 58 , respectively. unless otherwise specified, the parameters given in table 58 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 16 . table 57. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximum rating specified in table 14 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 14 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+ 8ma 2.7 v v dd 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v v dd 3.6 v -1.3 (4) 4. based on characterization data. v v oh (3) output high level voltage for an i/o pin v dd ?1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v v dd 3.6 v -0.4 (4) v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v v dd 3.6v -0.4 (5) 5. guaranteed by design. v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (5) - table 58. i/o ac characteristics (1)(2) ospeedr y[1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.7 v - - 8 c l = 10 pf, v dd 1.8 v - - 4 c l = 10 pf, v dd 1.7 v - - 3 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v --100ns electrical characteristics stm32f446xc/e 122/202 docid027107 rev 6 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 25 mhz c l = 50 pf, v dd 1.8 v - - 12.5 c l = 50 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.7 v - - 50 c l = 10 pf, v dd 1.8 v - - 20 c l = 10 pf, v dd 1.7 v - - 12.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 10 pf, v dd 2.7 v - - 6 c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.7 v - - 50 (4) mhz c l = 10 pf, v dd 2.7 v - - 100 (4) c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 1.8 v - - 50 c l = 10 pf, v dd 1.7 v - - 42.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.7 v - - 6 ns c l = 10 pf, v dd 2.7 v - - 4 c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 1.7 v - - 6 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.7 v - - 100 (4) mhz c l = 30 pf, v dd 1.8 v - - 50 c l = 30 pf, v dd 1.7 v - - 42.5 c l = 10 pf, v dd 2.7 v - - 180 (4) c l = 10 pf, v dd 1.8 v - - 100 c l = 10 pf, v dd 1.7 v - - 72.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.7 v - - 4 ns c l = 30 pf, v dd 1.8 v - - 6 c l = 30 pf, v dd 1.7 v - - 7 c l = 10 pf, v dd 2.7 v - - 2.5 c l = 10 pf, v dd 1.8 v - - 3.5 c l = 10 pf, v dd 1.7 v - - 4 -t extipw pulse width of external signals detected by the exti controller -10--ns table 58. i/o ac characteristics (1)(2) (continued) ospeedr y[1:0] bit value (1) symbol parameter conditions min typ max unit docid027107 rev 6 123/202 stm32f446xc/e electrical characteristics 175 figure 32. i/o ac charac teristics definition 6.3.18 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 56: i/o static characteristics ). unless otherwise specified, the parameters given in table 59 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 16 . 1. guaranteed by design. 2. the i/o speed is configured using the o speedry[1:0] bits. refer to the stm32f4x x reference manual fo r a description of the gpiox_speedr gpio port output speed register. 3. the maximum frequency is defined in figure 32 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 59. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design. electrical characteristics stm32f446xc/e 124/202 docid027107 rev 6 figure 33. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 59 . otherwise the reset is not taken into account by the device. 3. the external capacitor on nrst must be placed as close as pos sible to the device. 6.3.19 tim time r characteristics the parameters given in table 60 are guaranteed by design. refer to section 6.3.17: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 6.3.20 communications interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl too are mapped as not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. d l f 6 7 0 ) 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o 5 h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 60. timx characteristics (1)(2) symbol parameter conditions (3) min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 180 mhz 1-t timxclk ahb/apbx prescaler>4, f timxclk = 90 mhz 1-t timxclk f ext timer external clock frequency on ch1 to ch4 f timxclk = 180 mhz 0f timxclk /2 mhz res tim timer resolution - 16/32 bit t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk 1. timx is used as a general term to refer to the tim1 to tim12 timers. 2. guaranteed by design. 3. the maximum timer frequency on apb1 or apb2 is up to 180 mh z, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, t hen timxclk = hckl, otherwise timxclk = 4x pclkx. docid027107 rev 6 125/202 stm32f446xc/e electrical characteristics 175 the i 2 c characteristics are described in table 61 . refer also to section 6.3.17: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . table 61. i 2 c characteristics symbol parameter standard mode i 2 c (1)(2) 1. guaranteed based on test during characterization. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time - 3450 (3) 3. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. -900 (4) 4. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. t v(sda, ack) data, ack valid time - 3.45 - 0.9 t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s t sp pulse width of the spikes that are suppressed by the analog filter for standard and fast mode - - 0.05 0.09 (5) 5. the minimum width of the spikes fi ltered by the analog filter is above t sp (max). s c b capacitive load for each bus line - 400 - 400 pf electrical characteristics stm32f446xc/e 126/202 docid027107 rev 6 figure 34. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i2c bus power supply. d l f 5 3 , e & e x v s ' ' b , & 6 7 0 ) [ [ 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ w k 6 7 $ w z 6 & / / w z 6 & / + w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' w v x 6 7 $ w v x 6 7 2 6 7 2 3 w z 6 7 2 6 7 $ s ' ' b , & 5 3 5 6 5 6 6 7 $ 5 7 6 7 $ 5 7 6 ' $ 6 & / docid027107 rev 6 127/202 stm32f446xc/e electrical characteristics 175 fmpi 2 c characteristics the fmpi2c characterist ics are described in table 62 . refer also to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). table 62. fmpi 2 c characteristics (1) - parameter standard mode fast mode fast+ mode unit min max min max min max f fmpi2cc f mpi2cclk frequency 2 - 8 - 17 16 (2) - us t w(scll) scl clock low time 4.7 - 1.3 - 0.5 - t w(sclh) scl clock high time 4.0 - 0.6 - 0.26 - t su(sda) sda setup time 0.25 - 0.10 - 0.05 - t h(sda) sda data hold time 0 - 0 - 0 - t v(sda,ack) data, ack valid time - 3.45 - 0.9 - 0.45 t r(sda) t r(scl) sda and scl rise time - 0.100 - 0.30 - 0.12 t f(sda) t f(scl) sda and scl fall time - 0.30 - 0.30 - 0.12 t h(sta) start condition hold time 4 - 0.6 - 0.26 - t su(sta) repeated start condition setup time 4.7 - 0.6 - 0.26 - t su(sto) stop condition setup time 4 - 0.6 - 0.26 - t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - 0.5 - t sp pulse width of the spikes that are suppressed by the analog filter for standard and fast mode - - 0.05 0.09 0.05 0.09 c b capacitive load for each bus line - 400 - 400 - 550 (3) pf 1. guaranteed based on test during characterization. 2. when tr(sda,scl)<=110ns. 3. can be limited. maximum supported value can be re trieved by referring to the following formulas: t r(sda/scl) = 0.8473 x r p x c load r p(min) = (v dd -v ol(max) ) / i ol(max) electrical characteristics stm32f446xc/e 128/202 docid027107 rev 6 figure 35. fmpi 2 c timing diagram and measurement circuit d l f 5 3 , e & e x v s ' ' b , & 6 7 0 ) [ [ 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ w k 6 7 $ w z 6 & / / w z 6 & / + w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' w v x 6 7 $ w v x 6 7 2 6 7 2 3 w z 6 7 2 6 7 $ s ' ' b , & 5 3 5 6 5 6 6 7 $ 5 7 6 7 $ 5 7 6 ' $ 6 & / docid027107 rev 6 129/202 stm32f446xc/e electrical characteristics 175 spi interface characteristics unless otherwise specified, the parameters given in table 63 for spi are derived from tests performed under the ambient temperature, fpclkx frequency and vdd supply voltage conditions su mmarized in table 16 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c=30pf ? measurement points are done at cmos levels: 0.5vdd refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 63. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master full duplex/receiver mode, 2.7 v v dd 3.6 v spi1/4 -- 45 mhz master transmitter 1.71v docid027107 rev 6 131/202 stm32f446xc/e electrical characteristics 175 figure 37. spi timing diagram - slave mode and cpha = 1 figure 38. spi timing diagram - master mode d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics stm32f446xc/e 132/202 docid027107 rev 6 qspi interface characteristics unless otherwise specified, the parameters given in table 64 for qspi are derived from tests performed under the ambient temperature, f ahb frequency and v dd supply voltage conditions su mmarized in table 16 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c=20pf ? measurement points are done at cmos levels: 0.5vdd refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics. table 64. qspi dynamic characteristics in sdr mode (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) qspi clock frequency write mode 1.71 v v dd 3.6 v cload = 15 pf --90 mhz read mode 2.7v docid027107 rev 6 135/202 stm32f446xc/e electrical characteristics 175 figure 39. i 2 s slave timing diagram (philips protocol) (1) 1. . lsb transmit/receive of the previous ly transmitted byte. no lsb transmit/r eceive is sent before the first byte. figure 40. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck input cpol = 0 cpol = 1 t c(ck) w s input s d transmit s d receive t w(ckh) t w(ckl) t su(w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b transmit bitn transmit l s b transmit ai14 88 1b l s b receive (2) l s b transmit (2) ck output cpol = 0 cpol = 1 t c(ck) ws output sd receive sd transmit t w(ckh) t w(ckl) t su(sd_mr) t v(sd_mt) t h(sd_mt) t h(ws) t h(sd_mr) msb receive bitn receive lsb receive msb transmit bitn transmit lsb transmit ai14884b t f(ck) t r(ck) t v(ws) lsb receive (2) lsb transmit (2) electrical characteristics stm32f446xc/e 136/202 docid027107 rev 6 sai characteristics unless otherwise specified, the parameters given in table 67 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and vdd supply voltage conditions su mmarized in table 16 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c=30 pf ? measurement points are performed at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (sck,sd,ws). (3) table 67. sai characteristics (1) symbol parameter conditions min max unit f mck sai main clock output - 256 x 8k 256 x fs mhz f ck sai clock frequency (2) master data: 32 bits - 128 x fs (3) mhz slave data: 32 bits - 128 x fs (3) t v(fs) fs valid time master mode 2.7 v v dd 3.6 v -14% master mode 1.71 v v dd 3.6 v -17.5 ns t h(fs) fs hold time master mode 7 - t su(fs) fs setup time slave mode 1 - t h(fs) fs hold time slave mode 1 - t su(sd_a_mr) data input setup time master receiver 1 - t su(sd_b_sr) slave receiver 1 - t h(sd_a_mr) data input hold time master receiver 5 - t h(sd_b_sr) slave receiver 1 - t v(sd_b_st) data output valid time slave trasmitter (after enable edge 2.7 v v dd 3.6 v -9.5 slave transmitter (after enable edge 1.71 v v dd 3.6 v -16 t h(sd_b_st) data output hold time slave transmitter (after enable edge 6 - t v(sd_b_st) data output valid time master transmitter (after enable edge 2.7 v v dd 3.6 v -15 master transmitter (after enable edge 1.71 v v dd 3.6 v -18 t h(sd_b_st) data output hold time master transmitter (after enable edge 7 - 1. guaranteed based on test during characterization. 2. 256xfs maximum corresponds to 45 mhz (apb2 xaximum frequency) 3. with fs = 192 khz docid027107 rev 6 137/202 stm32f446xc/e electrical characteristics 175 figure 41. sai master timing waveforms figure 42. sai slave timing waveforms usb otg full speed (fs) characteristics this interface is present in both the usb otg hs and usb otg fs controllers. table 68. usb otg full speed startup time symbol parameter max unit t startup (1) 1. guaranteed by design. usb otg full speed transceiver startup time 1 s - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 o u t p u t f 3 # + 3 ! ) ? 3 $ ? 8 t r a n s m i t t v & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t h & 3 3 l o t n t v 3 $ ? - 4 t h 3 $ ? - 4 3 l o t n t s u 3 $ ? - 2 t h 3 $ ? - 2 - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 i n p u t 3 ! ) ? 3 $ ? 8 t r a n s m i t t s u & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t w # + ( ? 8 t h & 3 3 l o t n t v 3 $ ? 3 4 t h 3 $ ? 3 4 3 l o t n t s u 3 $ ? 3 2 t w # + , ? 8 t h 3 $ ? 3 2 f 3 # + electrical characteristics stm32f446xc/e 138/202 docid027107 rev 6 note: when vbus sensing feature is enabled, pa9 and pb13 should be left at their default state (floating input), not as alternate function. a typical 200 a current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on pa9 and pb13 when the feature is enabled. figure 43. usb otg full speed timings: definition of data signal rise and fall time table 69. usb otg full speed dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v ddusb usb otg full speed transceiver operating voltage -3.0 (2) 2. the usb otg full speed transceiver functionality is ensured down to 2.7 v but not the full usb full speed electrical characteri stics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold -1.3-2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg full speed drivers. --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v ddusb 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55 d l w i 6 6 w u 9 & 5 6 9 ' l i i h u h q w l d o g d w d o l q h v & u r v v r y h u s r l q w v docid027107 rev 6 139/202 stm32f446xc/e electrical characteristics 175 usb high speed (hs) characteristics unless otherwise specified, the parameters given in table 73 for ulpi are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 72 and v dd supply voltage cond itions summarized in table 71 , with the following configuration: ? output speed is set to ospeedry[1 :0] = 10, unless ot herwise specified ? capacitive load c = 30 pf, unless otherwise specified ? measurement points are done at cmos levels: 0.5v dd . refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. table 70. usb otg full speed electrical characteristics (1) 1. guaranteed by design. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crosso ver voltage - 1.3 2.0 v z drv output driver impedance (3) 3. no external termination series resistors are requ ired on dp (d+) and dm (d-) pins since the matching impedance is included in the embedded driver. driving high or low 28 44 table 71. usb hs dc elect rical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 1.7 3.6 v table 72. usb hs cloc k timing parameters (1) symbol parameter min typ max unit - f hclk value to guarantee proper operation of usb hs interface 30 - - mhz f start_8bit frequency (first transition) 8-bit 10% 54 60 66 mhz f steady frequency (steady state) 500 ppm 59.97 60 60.03 mhz d start_8bit duty cycle (first transition) 8-bit 10% 40 50 60 % d steady duty cycle (steady state) 500 ppm 49.975 50 50.025 % t steady time to reach the steady state frequency and duty cycle after the first transition --1.4ms electrical characteristics stm32f446xc/e 140/202 docid027107 rev 6 figure 44. ulpi timing diagram can (controller area network) interface refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (canx_tx and canx_rx). t start_dev clock startup time after the de-assertion of suspendm peripheral - - 5.6 ms t start_host host - - - t prep phy preparation time after the first transition of the input clock ---s 1. guaranteed by design. table 72. usb hs clock timing parameters (1) (continued) symbol parameter min typ max unit # l o c k # o n t r o l ) n 5 , 0 ) ? $ ) 2 5 , 0 ) ? . 8 4 d a t a ) n b i t # o n t r o l o u t 5 , 0 ) ? 3 4 0 d a t a o u t b i t t $ $ t $ # t ( $ t 3 $ t ( # t 3 # a i c t $ # table 73. dynamic characteristics: usb ulpi (1) symbol parameter conditions min. typ. max. unit t sc control in (ulpi_dir, ulpi_nxt) setup time - 1 - - ns t hc control in (ulpi_dir, ulpi_nxt) hold time - 1.5 - - t sd data in setup time - 1.5 - - t hd data in hold time - 1.5 - - t dc /t dd data/control output delay 2.7 v < v dd < 3.6 v, c l = 20 pf -68.5 1.71 v < v dd < 3.6 v, c l = 15 pf -611.5 1. guaranteed based on test during characterization. docid027107 rev 6 141/202 stm32f446xc/e electrical characteristics 175 6.3.21 12-bit adc characteristics unless otherwise specified, the parameters given in table 74 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 16 . table 74. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) -3.6 v v ref+ positive reference voltage 1.7 (1) -v dda v ref- negative reference voltage - - 0 - f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 mhz f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz ---171/f adc v ain conversion voltage range (3) - 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details --50 ? r adc (2)(4) sampling switch resistance - - - 6 ? c adc (2) internal sample and hold capacitor --47pf t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s ---3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s ---2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s - 3 - 480 1/f adc t stab (2) power-up time - - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc electrical characteristics stm32f446xc/e 142/202 docid027107 rev 6 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (2) adc v ref dc current consumption in conversion mode - - 300 500 a i vdda (2) adc v dda dc current consumption in conversion mode --1.61.8ma 1. v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). 2. guaranteed based on test during characterization. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 74 . table 74. adc characteristics (continued) symbol parameter conditions min typ max unit table 75. adc static accuracy at f adc = 18 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed based on test during characterization. unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 r ain k0.5 ? () f adc c adc 2 n 2 + () ln r adc ? = docid027107 rev 6 143/202 stm32f446xc/e electrical characteristics 175 a note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion table 76. adc static accuracy at f adc = 30 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed based on test during characterization. unit et total unadjusted error f adc = 30 mhz, r ain < 10 k , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 table 77. adc static accuracy at f adc = 36 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. guaranteed based on test during characterization. unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6 table 78. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion - 67 - 72 - 1. guaranteed based on test during characterization. table 79. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion - 70 - 72 - 1. guaranteed based on test during characterization. electrical characteristics stm32f446xc/e 144/202 docid027107 rev 6 being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.17 does not affect the adc accuracy. figure 45. adc accuracy characteristics 1. see also table 76 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. a i c % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , docid027107 rev 6 145/202 stm32f446xc/e electrical characteristics 175 figure 46. typical connecti on diagram using the adc 1. refer to table 74 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. d l 6 7 0 ) 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u electrical characteristics stm32f446xc/e 146/202 docid027107 rev 6 general pcb design guidelines power supply decoupling should be performed as shown in figure 47 or figure 48 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 47. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga144. v ref+ is also available on lqfp100, lqfp144, and wlcsp81. when v ref+ and v ref? are not available, they are internally connected to v dda and v ssa . 6 7 0 ) ? ) q ) ? ) q ) 9 5 ( ) 9 ' ' $ 9 6 6 $ 9 5 ( ) d l e docid027107 rev 6 147/202 stm32f446xc/e electrical characteristics 175 figure 48. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga144. v ref+ is also available on lqfp100, lqfp144, and wlcsp81. when v ref+ and v ref? are not available, they are internally connected to v dda and v ssa . 6.3.22 temperature sensor characteristics 6 7 0 ) ? ) q ) d l f 9 5 ( ) 9 ' ' $ 9 5 ( ) 9 6 6 $ table 80. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 - mv/c v 25 (1) voltage at 25 c - 0.76 - v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. guaranteed based on test during characterization. 2. guaranteed by design. table 81. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1fff 7a2e - 0x1fff 7a2f electrical characteristics stm32f446xc/e 148/202 docid027107 rev 6 6.3.23 v bat monitoring characteristics 6.3.24 reference voltage the parameters given in table 83 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 16 . 6.3.25 dac electri cal characteristics table 82. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 4 - - er (1) error on q - 1 - + 1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design. 2. shortest sampling time can be determined in the application by multiple iterations. table 83. internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -10--s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3v 10mv - 3 5 mv t coeff (2) temperature coefficient - - 30 50 ppm/c t start (2) startup time - - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design. table 84. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c vdda = 3.3 v 0x1fff 7a2a - 0x1fff 7a2b table 85. dac characteristics symbol parameter conditions min typ max unit comments v dda analog supply voltage -1.7 (1) -3.6 v - v ref+ reference supply voltage -1.7 (1) -3.6vv ref+ v dda docid027107 rev 6 149/202 stm32f446xc/e electrical characteristics 175 v ssa ground - 0 - 0 v - r load (2) resistive load dac output buffer on connected to v ssa 5- - k - connected to v dda 25 - - - r o (2) impedance output with buffer off ---15k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on -0.2 --v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.7 v dac_out max (2) higher dac_out voltage with buffer on --- v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off --0.5-mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off --- v ref + ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) - - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs --5075 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (4) dac dc vdda current consumption in quiescent mode (3) - - 280 380 a with no load, middle code (0x800) on the inputs - - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code- 1lsb) - - - 0.5 lsb given for the dac in 10-bit configuration. ---2 lsb given for the dac in 12-bit configuration. table 85. dac characteristics (continued) symbol parameter conditions min typ max unit comments electrical characteristics stm32f446xc/e 150/202 docid027107 rev 6 inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) ---1lsb given for the dac in 10-bit configuration. ---4lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) ---10mv given for the dac in 12-bit configuration ---3lsb given for the dac in 10-bit at v ref+ = 3.6 v - - - 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - - 0.5 % given for the dac in 12-bit configuration t settling (4 ) total harmonic distortion buffer on --36s c load 50 pf, r load 5 k thd (4) -----db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) ---1 ms/ s c load 50 pf, r load 5 k t wakeup (4) wakeup time from off state (setting the enx bit in the dac control register) --6.510s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - - - 67 - 40 db no r load , c load = 50 pf 1. v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.16.2: internal reset off ). 2. guaranteed by design. 3. the quiescent mode corresponds to a state where the dac ma intains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed based on test during characterization. table 85. dac characteristics (continued) symbol parameter conditions min typ max unit comments docid027107 rev 6 151/202 stm32f446xc/e electrical characteristics 175 figure 49. 12-bit buffered/non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u % x i i h u h g q r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 5 / 2 $ ' & / 2 $ ' d l g electrical characteristics stm32f446xc/e 152/202 docid027107 rev 6 6.3.26 fmc characteristics unless otherwise specified, the parameters given in table 86 to table 93 for the fmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage conditions summarized in table 15 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitance load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. asynchronous waveforms and timings figure 50 through figure 53 represent asynchronous waveforms and table 86 through table 93 provide the corresponding ti mings. the results shown in these tables are obtained with the following fm c configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode , datasetuptime = 0x5) ? busturnaroundduration = 0x0 in all timing tables, the t hclk is the hclk clock period. docid027107 rev 6 153/202 stm32f446xc/e electrical characteristics 175 figure 50. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. $ a t a & - # ? . % & - # ? . " , ; = & - # ? $ ; = t v " , ? . % t h $ a t a ? . % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t s u $ a t a ? . % t w . % - 3 6 w . / % t t v . / % ? . % t h . % ? . / % t h $ a t a ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f446xc/e 154/202 docid027107 rev 6 table 86. asynchronous non-multiplexed sram/psram/nor - read timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 2t hclk ? 2 2 t hclk + 0.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 0 1 t w(noe) fmc_noe low time 2t hclk - 1 2t hclk + 0.5 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 0.5 t h(a_noe) address hold time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t h(bl_noe) fmc_bl hold time after fmc_noe high 0 - t su(data_ne) data to fmc_nex high setup time t hclk - 2 - t su(data_noe) data to fmc_noex high setup time t hclk - 2 - t h(data_noe) data hold time after fmc_noe high 0 - t h(data_ne) data hold time after fmc_nex high 0 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk +1 table 87. asynchronous non-multiplexed sram/psram/nor read - nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 7t hclk + 1 7t hclk ns t w(noe) fmc_nwe low time 5t hclk ? 1 5t hclk + 1 t w(nwait) fmc_nwait low time t hclk ? 0.5 - t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk + 1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk + 1 - docid027107 rev 6 155/202 stm32f446xc/e electrical characteristics 175 figure 51. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. table 88. asynchronous non-multipl exed sram/psram/nor write timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 3 t hclk - 2 3 t hclk +0.5 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 0.5 t hclk + 0.5 t w(nwe) fmc_nwe low time t hclk t hclk + 0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk + 0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 0 t h(a_nwe) address hold time after fmc_nwe high t hclk - 0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 1 t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk + 0.5 - t v(data_ne) data to fmc_nex low to data valid - t hclk + 2 t h(data_nwe) data hold time after fmc_nwe high t hclk + 0.5 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk + 0.5 . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v $ a t a ? . % t w . % - 3 6 & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f446xc/e 156/202 docid027107 rev 6 figure 52. asynchronous multiplexed psram/nor read waveforms table 89. asynchronous non-multiplexed sram/psram/nor write - nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk - 0.5 8t hclk + 1 ns t w(nwe) fmc_nwe low time 6t hclk - 0.5 6t hclk + 1 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk - 0.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk + 2 - . " , $ a t a & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t v ! ? . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t s u $ a t a ? . % t h ! $ ? . ! $ 6 & - # ? . % & - # ? . / % t w . % t w . / % t v . / % ? . % t h . % ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % t h $ a t a ? . / % & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 docid027107 rev 6 157/202 stm32f446xc/e electrical characteristics 175 table 90. asynchronous multiplexed psram/nor read timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk ? 2 3t hclk +0.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 2t hclk ? 0.5 2t hclk t tw(noe) fmc_noe low time t hclk ? 1 t hclk + 0.5 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 2 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 2 t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk + 0.5 t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high) 0 - t h(a_noe) address hold time after fmc_noe high t hclk ? 0.5 - t h(bl_noe) fmc_bl time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t su(data_ne) data to fmc_nex high setup time t hclk + 1.5 - t su(data_noe) data to fmc_noe high setup time t hclk + 1 - t h(data_ne) data hold time after fmc_nex high 0 - t h(data_noe) data hold time after fmc_noe high 0 - table 91. asynchronous multiplexed psram/nor read-nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk - 1 8t hclk + 2 ns t w(noe) fmc_nwe low time 5t hclk ? 1 5t hclk + 1 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk + 1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk + 1 - electrical characteristics stm32f446xc/e 158/202 docid027107 rev 6 figure 53. asynchronous multip lexed psram/nor write waveforms . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v ! ? . % t w . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t v $ a t a ? . ! $ 6 t h ! $ ? . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 docid027107 rev 6 159/202 stm32f446xc/e electrical characteristics 175 synchronous waveforms and timings figure 54 through figure 57 represent synchronous waveforms and table 94 through table 97 provide the corresponding ti mings. the results shown in these tables are obtained with the following fm c configuration: ? burstaccessmode = fmc_ burstaccessmode_enable; ? memorytype = fmc_memorytype_cram; ? writeburst = fmc_writeburst_enable; ? clkdivision = 1; (0 is not supported, see the stm32f446 reference manual: rm0390) ? datalatency = 1 for nor flash; datalatency = 0 for psram table 92. asynchronous multiplexed psram/nor write timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 4t hclk - 2 4t hclk +0.5 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk t hclk + 0.5 t w(nwe) fmc_nwe low time 2t hclk 2t hclk + 0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk - t v(a_ne) fmc_nex low to fmc_a valid - 0 t v(nadv_ne) fmc_nex low to fmc_nadv low 0.5 1 t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk + 0.5 t h(ad_nadv) fmc_ad(adress) valid hold time after fmc_nadv high) t hclk ? 2 - t h(a_nwe) address hold time after fmc_nwe high t hclk - t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk ?2 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t v(data_nadv) fmc_nadv high to data valid - t hclk + 1.5 t h(data_nwe) data hold time after fmc_nwe high t hclk + 0.5 - table 93. asynchronous multiplexed psram/nor write-nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(ne) fmc_ne low time 9t hclk 9t hclk + 0.5 ns t w(nwe) fmc_nwe low time 7t hclk 7t hclk + 2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk + 1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk ? 1 - electrical characteristics stm32f446xc/e 160/202 docid027107 rev 6 in all timing tables, the t hclk is the hclk clock period (with maximum fmc_clk = 90 mhz). figure 54. synchronous multiplexed nor/psram read timings & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . / % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 docid027107 rev 6 161/202 stm32f446xc/e electrical characteristics 175 table 94. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2.5 t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk - 0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 2 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 0.5 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 1 - t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 3.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 1 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 - electrical characteristics stm32f446xc/e 162/202 docid027107 rev 6 figure 55. synchronous multiplexed psram write timings & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . 7 % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + ( . 7 % ( t d # , + , . 7 % , t d # , + ( . " , ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 t d # , + , $ a t a & - # ? . " , docid027107 rev 6 163/202 stm32f446xc/e electrical characteristics 175 table 95. synchronous multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(clk) fmc_clk period, vdd range= 2.7 to 3.6 v 2t hclk - 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk + 0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 2 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 0 t (clkh-nweh) fmc_clk high to fmc_nwe high t hclk - 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low - 3 t d(clkl-nbll) fmc_clk low to fmc_nbl low 0 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk - 0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 - electrical characteristics stm32f446xc/e 164/202 docid027107 rev 6 figure 56. synchronous non-multiplexed nor/psram read timings table 96. synchronous non-multipl exed nor/psram read timings (1)(2) symbol parameter min max unit t w(clk) fmc_clk period 2t hclk - ns t (clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk ? 0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 2 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - t su(dv-clkh) fmc_d[15:0] valid data before fmc_clk high 1 - t h(clkh-dv) fmc_d[15:0] valid data after fmc_clk high 3.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 1 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 - & - # ? # , + & - # ? . % x & - # ? ! ; = & - # ? . / % & - # ? $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y t d # , + , . % x , t d # , + ( . % x ( t d # , + , ! 6 t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t s u $ 6 # , + ( t h # , + ( $ 6 t s u $ 6 # , + ( t h # , + ( $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 & - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( docid027107 rev 6 165/202 stm32f446xc/e electrical characteristics 175 figure 57. synchronous non-multi plexed psram write timings 1. c l = 30 pf. 2. guaranteed based on test during characterization. - 3 6 & - # ? # , + & - # ? . % x & - # ? ! ; = & - # ? . 7 % & - # ? $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y t d # , + , . % x , t d # , + ( . % x ( t d # , + , ! 6 t d # , + ( ! ) 6 t d # , + ( . 7 % ( t d # , + , . 7 % , t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 & - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( t d # , + , $ a t a & - # ? . " , t d # , + ( . " , ( electrical characteristics stm32f446xc/e 166/202 docid027107 rev 6 nand controller waveforms and timings figure 58 through figure 61 represent synchronous waveforms, and table 98 and table 99 provide the corresponding timings. the results shown in this table are obtained with the following fmc configuration: ? com.fsmc_setuptime = 0x01; ? com.fmc_waitsetuptime = 0x03; ? com.fmc_holdsetuptime = 0x02; ? com.fmc_hizsetuptime = 0x01; ? att.fmc_setuptime = 0x01; ? att.fmc_waitsetuptime = 0x03; ? att.fmc_holdsetuptime = 0x02; ? att.fmc_hizsetuptime = 0x01; ? bank = fmc_bank_nand; ? memorydatawidth = fmc_memorydatawidth_16b; ? ecc = fmc_ecc_enable; ? eccpagesize = fmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. table 97. synchronous non-multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk ? 0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 2 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 3 t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk + 1 - t d(clkl-data) fmc_d[15:0] valid data after fmc_clk low - 2.5 t d(clkl-nbll) fmc_clk low to fmc_nbl low 3 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk + 1.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 1.5 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 - docid027107 rev 6 167/202 stm32f446xc/e electrical characteristics 175 figure 58. nand controller waveforms for read access figure 59. nand controller waveforms for write access & - # ? . 7 % & - # ? . / % . 2 % & - # ? $ ; = t s u $ . / % t h . / % $ - 3 6 ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % - 3 6 t h . 7 % $ t v . 7 % $ & - # ? . 7 % & - # ? . / % . 2 % & - # ? $ ; = ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . 7 % t h . 7 % ! , % electrical characteristics stm32f446xc/e 168/202 docid027107 rev 6 figure 60. nand controller waveforms for common memory read access figure 61. nand controller wavefo rms for common memory write access table 98. switching ch aracteristics for nand flash read cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(n0e) fmc_noe low width 4t hclk ? 0.5 4t hclk + 0.5 ns t su(d-noe) fmc_d[15-0] valid data before fmc_noe high 9 - t h(noe-d) fmc_d[15-0] valid data after fmc_noe high 2.5 - t d(ale-noe) fmc_ale valid before fmc_noe low - 3t hclk - 0.5 t h(noe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 2 - - 3 6 & - # ? . 7 % & - # ? . / % & - # ? $ ; = t w . / % t s u $ . / % t h . / % $ ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % - 3 6 t w . 7 % t h . 7 % $ t v . 7 % $ & - # ? . 7 % & - # ? . / % & - # ? $ ; = t d $ . 7 % ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % docid027107 rev 6 169/202 stm32f446xc/e electrical characteristics 175 sdram waveforms and timings figure 62. sdram read access waveforms (cl = 1) table 99. switching characteristics for nand flash write cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(nwe) fmc_nwe low width 4t hclk - 2 4t hclk ns t v(nwe-d) fmc_nwe low to fmc_d[15-0] valid 0 - ns t h(nwe-d) fmc_nwe high to fmc_d[15-0] invalid 3t hclk ? 1 - ns t d(d-nwe) fmc_d[15-0] valid before fmc_nwe high 5t hclk ? 3 - ns t d(ale-nwe) fmc_ale valid before fmc_nwe low - 3t hclk - 0.5 ns t h(nwe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 2 - ns - 3 6 2 o w n # o l & - # ? 3 $ # , + & - # ? ! > @ & - # ? 3 $ . 2 ! 3 & - # ? 3 $ . # ! 3 & - # ? 3 $ . 7 % & - # ? $ ; = & - # ? 3 $ . % ; = t d 3 $ # , + , ? ! d d 2 t d 3 $ # , + , ? ! d d # t h 3 $ # , + , ? ! d d 2 t h 3 $ # , + , ? ! d d # t d 3 $ # , + , ? 3 . $ % t s u 3 $ # , + ( ? $ a t a t h 3 $ # , + ( ? $ a t a # o l # o l i # o l n $ a t a $ a t a i $ a t a n $ a t a t h 3 $ # , + , ? 3 . $ % t d 3 $ # , + , ? . 2 ! 3 t d 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . 2 ! 3 electrical characteristics stm32f446xc/e 170/202 docid027107 rev 6 table 100. sdram read timings (1)(2) 1. cl = 30 pf on data and address lines. cl=15pf on fmc_sdclk . 2. guaranteed based on test during characterization. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk - 0.5 2t hclk +0.5 ns t su(sdclkh _data) data input setup time 1 - t h(sdclkh_data) data input hold time 4 - t d(sdclkl_add) address valid time - 3 t d(sdclkl_ sdne) chip select valid time - 1.5 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 1.5 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t h(sdclkl_sdncas) sdncas hold time 0 - table 101. lpsdr sdram read timings (1)(2) 1. cl = 10 pf . 2. guaranteed based on test during characterization. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk - 0.5 2t hclk + 0.5 ns t su(sdclkh _data) data input setup time 1 - t h(sdclkh_data) data input hold time 5 - t d(sdclkl_add) address valid time - 3 t d(sdclkl_ sdne) chip select valid time - 3 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 2 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 2 t h(sdclkl_sdncas) sdncas hold time 0 - docid027107 rev 6 171/202 stm32f446xc/e electrical characteristics 175 figure 63. sdram write access waveforms table 102. sdram write timings (1)(2) 1. c l = 10 pf on data and address line. c l =15 pf on fmc_sdclk. 2. guaranteed based on test during characterization. symbol parameter min max unit f (sdclk) frequency of operation - 90 mhz t w(sdclk) fmc_sdclk period 2t hclk - 0.5 2t hclk + 0.5 ns t d(sdclkl _data) data output valid time - 2 t h(sdclkl _data) data output hold time 0.5 - t d(sdclk _add) address valid time - 3 t d(sdclkl _sdnwe)) sdnwe valid time - 1.5 t h(sdclkl_sdnwe)) sdnwe hold time 0 - t d(sdclkl_sdne)) chip select valid time - 1.5 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valie time - 1 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 1 t h(sdclkl_sdncas) sdncas hold time 0 - - 3 6 2 o w n # o l & - # ? 3 $ # , + & - # ? ! > @ & - # ? 3 $ . 2 ! 3 & - # ? 3 $ . # ! 3 & - # ? 3 $ . 7 % & - # ? $ ; = & - # ? 3 $ . % ; = t d 3 $ # , + , ? ! d d 2 t d 3 $ # , + , ? ! d d # t h 3 $ # , + , ? ! d d 2 t h 3 $ # , + , ? ! d d # t d 3 $ # , + , ? 3 . $ % t d 3 $ # , + , ? $ a t a t h 3 $ # , + , ? $ a t a # o l # o l i # o l n $ a t a $ a t a i $ a t a n $ a t a t h 3 $ # , + , ? 3 . $ % t d 3 $ # , + , ? . 2 ! 3 t d 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . 2 ! 3 t d 3 $ # , + , ? . 7 % t h 3 $ # , + , ? . 7 % & - # ? . " , ; = t d 3 $ # , + , ? . " , electrical characteristics stm32f446xc/e 172/202 docid027107 rev 6 6.3.27 camera interface (d cmi) timing specifications unless otherwise specified, the parameters given in table 104 for dcmi are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage summarized in table 16 , with the following configuration: ? dcmi_pixclk polarity: falling ? dcmi_vsync and dcmi_hsync polarity: high ? data formats: 14 bits table 103. lpsdr sdram write timings (1)(2) 1. cl = 10 pf. 2. guaranteed based on test during characterization. symbol parameter min max unit f (sdclk) frequency of operation - 84 mhz t w(sdclk) fmc_sdclk period 2t hclk - 0.5 2t hclk + 0.5 ns t d(sdclkl _data) data output valid time - 5 t h(sdclkl _data) data output hold time 0.5 - t d(sdclk _add) address valid time - 3 t d(sdclkl _sdnwe)) sdnwe valid time - 3 t h(sdclkl_sdnwe)) sdnwe hold time 0 - t d(sdclkl_sdne)) chip select valid time - 2.5 t h(sdclkl_ sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 2 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 2 t d(sdclkl_sdncas) sdncas hold time 0 - table 104. dcmi characteristics symbol parameter min max unit - frequency ratio dcmi_pixclk/f hclk -0.4 - dcmi_pixclk pixel clock input - 54 mhz d pixel pixel clock input duty cycle 30 70 % t su(data) data input setup time 1 - ns t h(data) data input hold time 3.5 - t su(hsync) t su(vsync) dcmi_hsync/dcmi_vsync input setup time 2 - t h(hsync) t h(vsync) dcmi_hsync/dcmi_vsync input hold time 0 - docid027107 rev 6 173/202 stm32f446xc/e electrical characteristics 175 figure 64. dcmi timing diagram 6.3.28 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 105 for the sdio are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 16 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. figure 65. sdio high-speed mode 0 6 9 ' & 0 , b 3 , ; & / . w v x 9 6 < 1 & w v x + 6 < 1 & ' & 0 , b + 6 < 1 & ' & 0 , b 9 6 < 1 & ' $ 7 $ > @ ' & 0 , b 3 , ; & / . w k + 6 < 1 & w k + 6 < 1 & w v x ' $ 7 $ w k ' $ 7 $ t 7 # + ( # + $ # - $ o u t p u t $ # - $ i n p u t t # t 7 # + , t / 6 t / ( t ) 3 5 t ) ( t f t r a i electrical characteristics stm32f446xc/e 174/202 docid027107 rev 6 figure 66. sd default mode a i # + $ # - $ o u t p u t t / 6 $ t / ( $ table 105. dynamic characteristics: sd / mmc characteristics (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time fpp =50mhz 9.5 10.5 - ns t w(ckh) clock high time fpp =50mhz 8.5 9.5 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp =50mhz 1 - - ns t ih input hold time hs fpp =50mhz 4.5 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs fpp =50mhz - 12.5 13 ns t oh output hold time hs fpp =50mhz 11 - - cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd fpp =25mhz 2.5 - - ns t ihd input hold time sd fpp =25mhz 5.5 - - cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd fpp =24mhz -3.54 ns t ohd output hold default time sd fpp =24mhz 2- - 1. guaranteed based on test during characterization. 2. v dd = 2.7 to 3.6 v. docid027107 rev 6 175/202 stm32f446xc/e electrical characteristics 175 6.3.29 rtc characteristics table 106. dynamic characteristics: emmc characteristics v dd = 1.7 v to 1.9 v (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time fpp =50mhz 9.5 10.5 - ns t w(ckh) clock high time fpp =50mhz 8.5 9.5 - cmd, d inputs (referenced to ck) in emmc mode t isu input setup time hs fpp =50mhz 0.5 - - ns t ih input hold time hs fpp =50mhz 7.5 - - cmd, d outputs (referenced to ck) in emmc mode t ov output valid time hs fpp =50mhz - 13.5 14.5 ns t oh output hold time hs fpp =50mhz 12 - - 1. guaranteed based on test during characterization. 2. v dd = 2.7 to 3.6 v. table 107. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4- package information stm32f446xc/e 176/202 docid027107 rev 6 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp64 package information figure 67. lqfp64-10x10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p table 108. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 docid027107 rev 6 177/202 stm32f446xc/e package information 199 figure 68. lqfp64 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 - 7.500 - - 0.2953 - e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 108. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c package information stm32f446xc/e 178/202 docid027107 rev 6 device marking for lqfp64 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 69. lqfp64 marking example (package top view) 1. parts marked as ?es?, "e" or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) $ < : : 5 h y l v l r q f r g h ' d w h f r g h 3 l q l g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q 5 ( 7 docid027107 rev 6 179/202 stm32f446xc/e package information 199 7.2 lqfp100 package information figure 70. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! table 109. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 package information stm32f446xc/e 180/202 docid027107 rev 6 figure 71. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 109. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c docid027107 rev 6 181/202 stm32f446xc/e package information 199 device marking for lqfp100 package the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 72. lqfp100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) 9 & 7 $ 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h : : < ' d w h f r g h 3 l q l g h q w l i l h u package information stm32f446xc/e 182/202 docid027107 rev 6 7.3 lqfp144 package information. figure 73. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # ! ? - % ? 6 ! ! ! , , c b ! h , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 * $ 8 * ( 3 / $ 1 ( p p ' ' ' ( ( ( . f f f & $ b 0 ( b 9 $ $ $ / / f e $ docid027107 rev 6 183/202 stm32f446xc/e package information 199 table 110. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.2 00 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.689 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package information stm32f446xc/e 184/202 docid027107 rev 6 figure 74. lqfp144 recommended footprint 1. dimensions are expr essed in millimeters. d l h docid027107 rev 6 185/202 stm32f446xc/e package information 199 device marking for lqfp144 package the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 75. lqfp144 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ' d w h f r g h 3 l q l g h q w l i l h u 6 7 0 ) = ( 7 $ 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h < : : 2 s w l r q d o j d w h p d u n package information stm32f446xc/e 186/202 docid027107 rev 6 7.4 ufbga144 7 x 7 mm package information figure 76. ufbga144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not in scale. table 111. ufbga144 - 144-pin, 7 x 7 mm , 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.11 0 0.0020 0.0031 0.0043 a2 0.400 0.450 0.50 0 0.0157 0.0177 0.0197 a3 - 0.130 - - 0.0051 - a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 b 0.230 0.280 0.320 0.0091 0.0110 0.0126 d 6.950 7.000 7.050 0 .2736 0.2756 0.2776 d1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - f 0.700 0.750 0.800 0.0276 0.0295 0.0315 $ $ 6 b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' 0 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : h $ $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d docid027107 rev 6 187/202 stm32f446xc/e package information 199 figure 77. ufbga144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 112. ufbga144 recommended pcb design rules (0.50 mm pitch bga) dimension recommended values pitch 0.50 mm dpad 0.280 mm dsm 0.370 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.280 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.120 mm table 111. ufbga144 - 144-pin, 7 x 7 mm , 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. ^z & wz s ' s d g ' v p package information stm32f446xc/e 188/202 docid027107 rev 6 device marking for ufbga144 7 x 7 mm packa ge the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 78. uqfp144 7 x 7 mm marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) < : : 3 u r g x f w l g h q w l i l f d w l r q $ g g l w l r q d o l q i r u p d w l r q ' d w h f r g h % d o o $ l q g h q w l i l h u = ( + $ docid027107 rev 6 189/202 stm32f446xc/e package information 199 7.5 ufbga144 10 x 10 mm package information figure 79. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 113. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.1 10 0.0020 0.0031 0.0043 a2 0.400 0.450 0.50 0 0.0157 0.0177 0.0197 a3 0.050 0.080 0.110 - 0.0051 - a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 b 0.360 0.400 0.440 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.2736 0.2756 0.2776 d1 8.750 8.800 8.850 0.2343 0.2362 0.2382 e 9.950 10.000 10.050 0.2736 0.2756 0.2776 e1 8.750 8.800 8.850 0.2343 0.2362 0.2382 e 0.750 0.800 0.850 - 0.0197 - $ < b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' 0 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : h $ $ % $ & g g g = ' ( h h h & $ % i i i ? ? 0 0 & $ $ $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d package information stm32f446xc/e 190/202 docid027107 rev 6 figure 80. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package recommended footprint f 0.550 0.600 0.650 0.0177 0.0197 0.0217 ddd - - 0.080 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 114. ufbga144 recommended pcb design rules (0.80 mm pitch bga) dimension recommended values pitch 0.80 mm dpad 0.400 mm dsm 0.550 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.400 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.120 mm table 113. ufbga144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. ? zz & wz s ' s d g ' v p docid027107 rev 6 191/202 stm32f446xc/e package information 199 device marking for ufbga144 10 x 10 mm packa ge the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 81. uqfp144 10 x 10 mm mark ing example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) < : : 3 u r g x f w l g h q w l i l f d w l r q $ g g l w l r q d o l q i r u p d w l r q ' d w h f r g h % d o o $ l q g h q w l i l h u = ( - $ package information stm32f446xc/e 192/202 docid027107 rev 6 7.6 wlcsp81 pac kage information figure 82. wlcsp81 - 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. table 115. wlcsp81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 0.600 - - 0.0236 a1 - 0.170 - - 0.0067 - a2 - 0.380 - - 0.0150 - a3 (2) - 0.025 - - 0.0010 - b (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 3.658 3.693 3.728 0.1440 0.1454 0.1468 e 3.780 3.815 3.850 0.1488 0.1502 0.1516 e - 0.400 - - 0.0157 - e1 - 3.200 - - 0.1260 - e2 - 3.200 - - 0.1260 - $ 7 b 0 ( b 9 7 r s y l h z : d i h u e d f n v l g h 6 l g h y l h z ' h w d l o $ % r w w r p y l h z % x p s v l g h $ e d o o o r f d w l r q $ ' h w d l o $ u r w d w h g e \ ? ' 6 h d w l q j s o d q h $ $ e ( h h h * ) h $ $ e d o o o r f d w l r q = d d d e e e = h h h = - $ ; < t g g g 0 = t f f f 0 = docid027107 rev 6 193/202 stm32f446xc/e package information 199 figure 83. wlcsp81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint f - 0.2465 - - 0.0097 - g - 0.3075 - - 0.0121 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. back side coating 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. table 116. wlcsp81 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 mm dpad 0.225 mm dsm 0.290 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.250 mm stencil thickness 0.100 mm table 115. wlcsp81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max $ 7 b ) 3 b 9 ' s d g ' v p package information stm32f446xc/e 194/202 docid027107 rev 6 device marking for wlcsp81 packa ge the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 84. wlcsp81 10 x 10 mm mark ing example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) < : : 3 u r g x f w l g h q w l i l f d w l r q $ g g l w l r q d o l q i r u p d w l r q ' d w h f r g h 3 l q l g h q w l i l h u 0 & < $ docid027107 rev 6 195/202 stm32f446xc/e package information 199 7.7 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 117. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm 46 c/w thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 42 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 33 thermal resistance junction-ambient ufbga144 - 7 7 mm / 0.5 mm pitch 51 thermal resistance junction-ambient ufbga144 - 10 10 mm / 0.8 mm pitch 48 thermal resistance junction-ambient wlcsp81 48 part numbering stm32f446xc/e 196/202 docid027107 rev 6 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 118. ordering information scheme example: stm32 f 446 v c t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 446= stm32f446xc/e, pin count m = 81 pins r = 64 pins v = 100 pins z = 144 pins flash memory size c=256 kbytes of flash memory e=512 kbytes of flash memory package h = ufbga (7 x 7 mm) j = ufbga (10 x 10 mm) t = lqfp y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel docid027107 rev 6 197/202 stm32f446xc/e application block diagrams 199 appendix a application block diagrams a.1 usb otg full speed (fs) interface solutions figure 85. usb controller configured as pe ripheral-only and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. figure 86. usb controller configured as host-only and used in full speed mode 1. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. 9 6 6 9 w r 9 ' ' 8 6 % 9 r o w d j h u h j x o d w r u 9 ' ' 8 6 % 2 6 & b , 1 2 6 & b 2 8 7 0 6 y 9 9 ' ' ' 3 3 $ 3 % 3 $ 3 % ' 0 8 6 % 6 w g % f r q q h f w r u 9 % 8 6 3 4 - & x x 6 $ $ 6 " 5 3 $ 0 6 3 3 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 - 3 6 # u r r e n t l i m i t e r p o w e r s w i t c h 0 ! 0 " 0 ! 0 " application block diagrams stm32f446xc/e 198/202 docid027107 rev 6 figure 87. usb controller configured in dual mode and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. the id pin is required in dual role only. 4. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. 3 4 - & x x 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 " 0 ! 0 " 0 ! 0 " 5 3 " m i c r o ! " c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r 6 t o 6 $ $ v o l t a g e r e g u l a t o r 6 $ $ ) $ 0 ! 0 " / 3 # ? ) . / 3 # ? / 5 4 - 3 6 # u r r e n t l i m i t e r p o w e r s w i t c h docid027107 rev 6 199/202 stm32f446xc/e application block diagrams 199 a.2 usb otg high speed (h s) interface solutions figure 88. usb controller configured as peripheral, host, or dual-mode and used in high speed mode 1. it is possible to use mco1 or mco2 to save a crystal. it is however not mandatory to clock the stm32f446xx with a 24 or 26 mhz crystal when us ing usb hs. the above figure only shows an example of a possible connection. 2. the id pin is required in dual role only. $ 0 3 4 - & x x $ - 6 " 5 3 6 3 3 $ - $ 0 ) $ 5 3 " 5 3 " ( 3 / 4 ' # t r l & 3 0 ( 9 5 , 0 ) ( i g h s p e e d / 4 ' 0 ( 9 5 , 0 ) ? # , + 5 , 0 ) ? $ ; = 5 , 0 ) ? $ ) 2 5 , 0 ) ? 3 4 0 5 , 0 ) ? . 8 4 n o t c o n n e c t e d c o n n e c t o r - # / o r - # / o r - ( z 8 4 0 , , 8 4 8 ) - 3 6 revision history stm32f446xc/e 200/202 docid027107 rev 6 revision history table 119. document revision history date revision changes 17-feb-2015 1 initial release. 16-mar-2015 2 added note 2 inside table 2 updated table 11 , table 23 , table 24 , table 25 , table 26 , table 30 , table 51 , table 52 , table 53 , and table 61 added condition inside typical and maximum current consumption and additional current consumption added fmpi2c characteristics added table 62 and figure 35 29-may-2015 3 updated: ? section 6.3.15: absolute maximum ratings (electrical sensitivity) ? section 7: package information ? table 2: stm32f446xc/e features and peripheral counts ? table 13: stm32f446xc/xe wlcsp81 ballout ? figure 53: esd absolute maximum ratings ? figure 54: synchronous multiple xed nor/psram read timings added: ? figure 78: uqfp144 7 x 7 mm marking example (package top view) , ? figure 81: uqfp144 10 x 10 mm marking example (package top view) , ? figure 84: wlcsp81 10 x 10 mm marking example (package top view) 10-aug-2015 4 updated: ? figure 14: stm32f446xc/xe ufbga144 ballout ? table 10: stm32f446xx pin and ball descriptions ? table 18: vcap_1/vcap_2 operating conditions ? section 3.15: power supply schemes ? section 6.3.2: vcap_1/vcap_2 external capacitor added: ? figure 5: vddusb connected to an external independent power supply ? notes 3 and 4 below figure 18: power supply scheme docid027107 rev 6 201/202 stm32f446xc/e revision history 201 03-nov-2015 5 updated: ? introduction ; ? table 2: stm32f446xc/e features and peripheral counts ? table 43: main pll characteristics ? title of table 45: pllisai characteristics ? table 109: lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data ? table 118: ordering information scheme ? figure 10: stm32f446xc/xe lqfp64 pinout ? figure 11: stm32f446xc/xe lqfp100 pinout added: ? figure 77: ufbga144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint ? figure 111: ufbga144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data 02-sep-2016 6 updated: ? section 7: package information ; ? table 30: typical current consum ption in run mode, code with data processing running from flash memory or ram, regulator on (art accelerator enabled except prefetch), vdd=1.7 v ? table 74: adc characteristics ? table 85: dac characteristics added: ? note 3 in figure 33: recommended nrst pin protection ? note 4 in table 41: hsi oscillator characteristics table 119. document revision history (continued) date revision changes stm32f446xc/e 202/202 docid027107 rev 6 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
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